Semiconductor Die Stacking with Conductive Pillars
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Solution Overview
Problem
Conventional semiconductor device stacking methods using leadframes face challenges such as increased manufacturing costs, degraded electrical performance due to long signal paths, and limitations in input/output pitch and pin count, particularly when attempting to stack multiple flipchip die vertically.
Innovation Solution
The method involves stacking semiconductor die with conductive pillars and bumps between the die and the substrate, allowing for reliable electrical connection and encapsulation, which reduces the footprint and enhances interconnectivity, thereby addressing the limitations of conventional wire-bonded and flipchip technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire-bonding is used to connect stacked die, then electrical connection is achieved, but signal path length increases degrading electrical performance
Solution Approach 1:
The patent transitions from planar wire-bonding to three-dimensional conductive pillar interconnection. Conductive pillars extend vertically through the substrate, enabling direct electrical connection between stacked die in the Z-dimension, thereby eliminating long lateral signal paths and reducing overall signal transmission distance.
Solution Approach 2:
Conductive pillars serve as intermediary structures that facilitate direct electrical connection between die. Instead of using long wire bonds that traverse lateral distances, the conductive pillars act as vertical conduits, providing a direct electrical pathway through the substrate and eliminating the need for extended wire bonds.
2Shape
If larger bumps are used for stacked die interconnect, then vertical stacking is enabled, but input/output pitch and pin count are limited
Solution Approach 1:
The patent segments the interconnection function into two distinct components: large bumps for mechanical support and vertical alignment, and conductive pillars for electrical connection. This segmentation allows the bumps to be optimized for stacking stability while the conductive pillars provide additional I/O pathways, thereby increasing overall pin count without compromising vertical stacking capability.
Solution Approach 2:
The conductive pillars serve multiple functions: they provide electrical connection, enable additional I/O pathways, and support vertical stacking. By making the interconnection system multi-functional, the patent overcomes the limitation where large bumps alone would restrict I/O pitch and pin count.
3Reliability
If conductive pillars are used for die interconnection, then electrical connection and compactness are improved, but manufacturing complexity increases
Solution Approach 1:
Conductive pillars are formed in the substrate before die mounting using established semiconductor fabrication techniques such as electroplating or electroless plating. This preliminary formation of conductive interconnect structures allows subsequent die stacking to proceed with standardized processes, reducing overall manufacturing complexity despite the added interconnection capability.
4Area of stationary object
If multiple die are stacked vertically, then footprint is reduced, but cantilever effects occur during wire-bonding process
Solution Approach 1:
The patent replaces the wire-bonding mechanical system with a conductive pillar-based electrical connection system. Conductive pillars are rigid, vertically-oriented structures that provide mechanical support and eliminate the cantilever effects associated with flexible wire bonds extending from overhanging die edges during the bonding process.
Data Source
AI summary
A semiconductor device has a first semiconductor die mounted to a first contact pad on a leadframe or substrate with bumps. A conductive pillar is formed over a second semiconductor die. The second die is mounted over the first die by electrically connecting the conductive pillar to a second contact pad on the substrate with bumps. The second die is larger than the first die. An encapsulant is deposited over the first and second die. Alternatively, the conductive pillars are formed over the substrate around the first die. A heat sink is formed over the second die, and a thermal interface material is formed between the first and second die. An underfill material is deposited under the first semiconductor die. A shielding layer is formed between the first and second die. An interconnect structure can be formed over the second contact pad of the substrate.