Semiconductor Package Stacking via Temporary Substrate
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Solution Overview
Problem
The vertical stacking of multiple flip chips in semiconductor manufacturing often results in defective dies within stacked die packages, leading to inefficient production and increased manufacturing time due to the need for individual processing of each package.
Innovation Solution
A method involving a temporary substrate with a mounting surface for temporarily bonding and stacking semiconductor chips, using conductive contacts and through silicon interconnects, followed by bonding and de-bonding processes to form chip stacks, which can then be separated and encapsulated, allowing for the selection of known good dies and reducing manufacturing time by processing at the wafer level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical stacking of multiple flip chips is performed at the wafer level with through silicon interconnects, then productivity is improved by batch processing, but reliability deteriorates due to defective dies in the wafer stack
Solution Approach 1:
The method segments the wafer-level stacking process into two distinct stages: (1) batch formation of multiple chip stacks on the wafer, and (2) individual singulation of each chip stack. This segmentation allows the benefits of batch processing to be realized while enabling quality control at the individual package level, as each chip stack can be evaluated and separated independently based on die quality.
Solution Approach 2:
The patent applies preliminary action by forming the complete chip stacks with through silicon interconnects at the wafer level before final singulation. This preliminary batch processing establishes the interconnect structure in advance, and subsequent singulation then separates the stacks into individual packages, allowing defective dies to be identified and isolated without affecting other stacks.
2Loss of time
If wafer level stacking is performed, then manufacturing time is reduced through batch processing, but device complexity increases due to the need for through silicon interconnects
Solution Approach 1:
The method merges multiple chip stacking operations into a single batch process at the wafer level. Multiple chip stacks are formed simultaneously on the wafer using shared through silicon interconnect structures, and then all stacks are singulated together. This merging approach reduces the number of separate processing steps compared to individual package assembly, thereby reducing manufacturing cycle time despite the complexity of the interconnect structure.
3Ease of manufacture
If chips are temporarily mounted on a temporary substrate and then separated, then ease of manufacture is improved through simplified assembly, but loss of time increases due to additional bonding and de-bonding steps
Solution Approach 1:
The patent introduces a temporary substrate as an intermediary carrier that facilitates the stacking and singulation processes. The temporary substrate provides a convenient platform for temporarily mounting chips, forming interconnects, and performing batch operations. The temporary nature of this substrate allows for easy removal after the stacking is complete, enabling simplified assembly operations without permanent fixtures.
Solution Approach 2:
The temporary substrate is designed to be discarded after serving its purpose in the stacking and singulation process. The bonding and de-bonding steps involve attaching chips to the temporary substrate and then removing them together as complete stacks. This approach accepts the temporary time investment in bonding/de-bonding in exchange for significantly simplified subsequent assembly operations, as the complete stacks are ready for final installation without further processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of stacked die semiconductor packages with reduced instances of defective packages and streamlined manufacturing by allowing known good dies to be selected and processed efficiently, while also simplifying assembly and enabling recycling of the base carrier.
Implementation Method 1
The through silicon interconnects may typically be formed by creating vias that extend from the inactive or backside of the chip to the active or front side of the chip, and subsequently filling the vias with a conductive material such as copper
Implementation Method 2
bonding the first and second chips together to form a plurality of chip stacks
Data Source
AI summary
A method of forming a device stack is presented. The method includes providing a temporary substrate having a temporary mounting surface. A first chip is temporarily mounted to the temporary mounting surface. A first bottom surface of the first chip is temporarily mounted to the temporary mounting surface and a first top surface of the first chip comprises first interconnects. A second chip is stacked on the first chip. The second chip includes second conductive contacts on the second bottom surface. The method also includes bonding the first and second chips together to form the device stack. The second conductive contacts are coupled to the first interconnects. The first bottom surface of the first chip is separated from the substrate to separate the chip stack from the substrate.