Semiconductor Structure with Stage Difference Surface
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Solution Overview
Problem
Conventional semiconductor structures face challenges in reducing overall thickness due to the height of bonding wires needed to connect a cover to a printed circuit board, which affects product competitiveness.
Innovation Solution
A semiconductor structure comprising a chip, nonmetal oxide layer, conductive pad, passivation layer, isolation layer, and conductive layer, where the isolation layer covers the passivation and nonmetal oxide layers, allowing the conductive layer to contact the conductive pad without increasing the structure's thickness, enabling flexible application and improved competitiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cover is located above the conductive pad to enable wire bonding, then the bonding wire can reach the printed circuit board, but the overall thickness of the semiconductor structure increases
Solution Approach 1:
The patent introduces a multi-level stage structure with different heights (first stage difference surface and second stage difference surface) to redistribute the vertical space. The conductive pad is positioned on a higher stage while the cover is on a lower stage, creating a stepped configuration that enables wire bonding without increasing the overall thickness footprint.
Solution Approach 2:
The semiconductor structure is divided into multiple stages or levels with different elevation surfaces. The chip structure includes a first stage difference surface and a second stage difference surface, creating segmented platforms that allow different components to occupy different vertical zones, thus resolving the thickness conflict.
2Ease of operation
If the bonding wire height is increased to reach through the cover, then wire bonding can be achieved, but it becomes difficult to reduce the overall thickness during packaging
Solution Approach 1:
Instead of increasing wire height vertically, the patent uses horizontal staging to create access pathways. The multi-stage surface configuration allows wires to traverse across different elevation levels, achieving bonding accessibility without compromising thickness reduction goals.
3Ease of operation
If the conventional structure with cover over conductive pad is used, then wire bonding is enabled, but product competitiveness is negatively affected due to increased thickness
Solution Approach 1:
The patent segments the chip surface into multiple functional stages, allowing the conductive pad, cover, and bonding wire to coexist in a compact multi-level configuration. This segmentation enables thin-profile wire bonding that maintains product competitiveness.
Data Source
AI summary
A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.