Semiconductor Device Staggering Refresh Bank Activation
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Solution Overview
Problem
Multi-channel semiconductor memory devices experience increased peak noise due to simultaneous refresh operations across all channels, leading to overlapping refresh times and elevated peak currents.
Innovation Solution
A semiconductor device with a comparator and delay decision unit that detects simultaneous refresh commands across channels, adjusting bank active times to prevent simultaneous activation and reduce peak noise by introducing a delay in the activation of banks within channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If all channels are simultaneously operated with sequential bank refresh, then each channel can be independently refreshed at intervals of predetermined time, but refresh times of respective channels overlap resulting in increased peak noise
Solution Approach 1:
The system performs preliminary detection of simultaneous refresh commands across multiple channels using a comparator before the actual bank activation occurs. When simultaneous refresh commands are detected, the delay decision unit pre-emptsively introduces a delay to prevent overlapping refresh operations, thereby eliminating peak noise before it can occur.
Solution Approach 2:
The patent implements dynamic adjustment of bank activation timing based on real-time detection of refresh command patterns. The delay circuit dynamically introduces variable delays depending on whether simultaneous refresh commands are detected, allowing the system to adaptively manage refresh operations across channels to prevent noise peaks while maintaining independent operation capability.
2Productivity
If banks are sequentially activated at intervals of predetermined time in response to refresh command, then refresh operation is completed, but simultaneous activation across channels causes peak current multiplication
Solution Approach 1:
The comparator detects simultaneous refresh commands in advance before bank activation occurs. This preliminary detection enables the delay decision unit to preemptively introduce delays that prevent simultaneous bank activations, thereby avoiding peak current multiplication while maintaining efficient sequential refresh operations.
Solution Approach 2:
The delay circuit acts as an intermediary between the refresh command and the bank activation signal. It introduces controlled delays based on the detection results from the comparator, mediating the timing relationship between channels to prevent simultaneous activations and the resulting peak current effects.
3Adaptability or versatility
If simultaneous refresh commands are input to all channels, then all channels are refreshed at the same time, but this causes overlapping refresh times and elevated peak noise
Solution Approach 1:
The comparator provides feedback about simultaneous refresh command conditions to the delay decision unit. This feedback mechanism enables the system to detect when all channels receive simultaneous refresh commands and automatically adjust timing through the delay circuit to prevent overlapping operations and peak noise generation.
Solution Approach 2:
The system dynamically adjusts bank activation timing based on real-time detection of simultaneous refresh patterns. When simultaneous refresh commands are detected across all channels, the delay circuit dynamically introduces variable delays to stagger bank activations, thereby maintaining simultaneous refresh capability while preventing noise peaks.
Data Source
AI summary
A semiconductor device includes a plurality of channels. Each of the channels includes a plurality of banks sequentially activated at intervals of a predetermined time in response to a refresh command; a comparator, when the refresh command is input to a corresponding channel, configured to detect whether the refresh command is applied to a contiguous channel; a delay decision unit configured to output a control signal to determine a bank active delay time in response to an output signal of the comparator; and a delay circuit configured to control an active delay time of the plurality of banks in response to an output signal of the delay decision unit.