Semiconductor Device With Staggered Column Regions
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Solution Overview
Problem
Existing semiconductor devices with super-junction structures face challenges in lowering ON-resistance and elevating avalanche resistance, as increased impurity concentration and epitaxial layer thickness can lead to higher ON-resistance and reduced avalanche resistance due to current flow through column and base regions, causing thermal destruction and dielectric breakdown.
Innovation Solution
The semiconductor device features a substrate with trench gates and column regions spaced apart in a staggered manner, where column regions are not formed under the trench gates, reducing their occupied area and maximizing the distance of breakdown current from the trench gates, thereby lowering ON-resistance and enhancing avalanche resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impurity concentration of the epitaxial layer is increased to lower ON-resistance, then the ON-resistance decreases, but the breakdown voltage capability is limited by the layer thickness
Solution Approach 1:
The device segments the current conduction path into two distinct regions: column regions for voltage blocking and inter-column regions for current conduction. This segmentation allows the epitaxial layer to be fully utilized for breakdown voltage while providing separate low-resistance paths for ON-state current, resolving the contradiction between thickness requirements for high voltage and impurity concentration requirements for low ON-resistance.
Solution Approach 2:
The patent applies local quality by creating regions with different impurity concentrations in specific locations. The column regions maintain low impurity concentration for high breakdown voltage, while the inter-column regions have higher impurity concentration for low ON-resistance. This localized differentiation allows simultaneous optimization of both voltage blocking and current conduction properties.
2Reliability
If column regions occupy larger area to improve breakdown voltage, then the breakdown resistance increases, but the area for drain current flow is narrowed, increasing ON-resistance
Solution Approach 1:
The device structure segments the epitaxial layer into alternating column regions and inter-column regions, where column regions provide voltage blocking and inter-column regions provide current conduction. This segmentation ensures that column regions do not occupy continuous areas that would block current flow, instead creating a patterned structure where both functions are simultaneously optimized.
Solution Approach 2:
Different regions are assigned different functional qualities: column regions have low impurity concentration for electric field modulation and voltage blocking, while inter-column regions have high impurity concentration for low-resistance current conduction. This local quality differentiation maximizes the effective area for both breakdown voltage and current flow without mutual interference.
3Area of stationary object
If trench gates are positioned closer to column regions to reduce area, then the device area decreases, but breakdown current may flow through trench gates causing dielectric breakdown and thermal destruction
Solution Approach 1:
The patent employs asymmetric positioning where trench gates are strategically located at specific distances from column regions, creating an optimized spatial relationship. This asymmetric arrangement ensures sufficient separation to prevent breakdown current from reaching trench gates while minimizing the overall device footprint, balancing area reduction with avalanche resistance maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces ON-resistance by widening the area for drain current flow and elevates avalanche resistance by minimizing dielectric breakdown and thermal destruction, achieving a balance between low ON-resistance and high breakdown voltage.
Implementation Method 1
Each column region 550 has a second conductivity type, and is formed in the epitaxial layer 510... the breakdown voltage of the transistor is determined by the thickness of the epitaxial layer 510, irrespective of the impurity concentration of the epitaxial layer 510
Implementation Method 2
when the transistor is turned off... a depletion layer spreads respectively at the interface between each base region 520 and the epitaxial layer 510, and at the interface between each column region 550 and the epitaxial layer 510
Data Source
AI summary
A semiconductor device of the present invention has a first-conductivity-type substrate having second-conductivity-type base regions exposed to a first surface thereof; trench gates provided to a first surface of the substrate; first-conductivity-type source regions formed shallower than the base regions; a plurality of second-conductivity-type column regions located between two adjacent trench gates in a plan view, while being spaced from each other in a second direction normal to the first direction; the center of each column region and the center of each base contact region fall on the center line between two trench gates; and has no column region formed below the trench gates.