Semiconductor Device Staggered Vias Power Delivery
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Solution Overview
Problem
High specification electronic devices with increasing switching speeds lead to higher power consumption, reducing battery life due to increased current driving capability, necessitating the reduction of power consumption in semiconductor devices.
Innovation Solution
A semiconductor device design that reduces resistance and heat generation by connecting a redistribution to the source and drain of a power integrated circuit, utilizing staggered vias and interdigitating conductive lines with overlapping conductive plates for efficient power transfer and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If switching speeds are increased to achieve high specification electronic devices, then processing capability is improved, but power consumption increases
Solution Approach 1:
The power supply network is segmented into multiple independent power lines (first power line, second power line, third power line) that can be independently optimized and controlled. This segmentation allows for localized power management, reducing overall power consumption while maintaining high switching speeds in critical areas.
Solution Approach 2:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by forming conductive plugs through the substrate thickness direction. This vertical dimension reduces the resistance and inductance of power delivery paths, enabling faster switching with lower power consumption.
2Speed
If current driving capability is increased to improve switching speeds, then processing performance is improved, but heat generation increases
Solution Approach 1:
Different regions of the substrate are provided with different power line configurations and conductive plug densities according to local power consumption requirements. High-performance regions receive enhanced power delivery with multiple conductive plugs, while low-power regions use simpler interconnection, optimizing heat distribution and reducing overall heat generation.
Solution Approach 2:
The conductive plugs are formed with curved sidewalls rather than straight vertical walls, creating a tapered structure that expands toward the first surface. This curved geometry increases the effective contact area between conductive plugs and conductive lines, improving heat dissipation efficiency while maintaining electrical performance.
3Loss of energy
If resistance of routing path is reduced to improve power efficiency, then power transfer efficiency is improved, but routing path length must be optimized
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive plugs that extend through the substrate thickness, creating short vertical power delivery paths. This three-dimensional approach dramatically reduces the resistance of power routing paths compared to traditional planar interconnection, achieving low resistance without increasing lateral routing path length.
Data Source
AI summary
A semiconductor device is provided that includes a substrate including a device region and a peripheral region surrounding the device region, a first interconnection including one or more first conductive lines extending in a first direction, a second interconnection including one or more second conductive lines extending in the first direction, the second interconnection spaced apart from the first interconnection, a first conductive plate and a second conductive plate spaced apart from each other, the first conductive plate corresponding to the first interconnection and the second conductive plate corresponding to the second interconnection, one or more first vias connecting the first conductive lines to the first conductive plate and overlapping the device region and one or more second vias connecting the second conductive lines to the second conductive plate, the second vias overlapping the device region and arranged in a staggered, alternating configuration with the one or more first vias.