Semiconductor Element Stair-Like Potential Barrier for Charge Transfer
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Solution Overview
Problem
Existing CMOS image sensors face challenges in achieving perfect charge transfer and accumulation with a small potential difference between potential valleys, requiring high impurity concentrations and power supply voltages, which can decrease sensitivity and increase dark current.
Innovation Solution
A semiconductor element design with a stair-like-shaped electronic-shuttering potential barrier between potential valleys, using a first and second MOS capacitor to control charge transfer and accumulation, allowing for efficient charge transfer even with a small potential difference, and a block layer to prevent electron diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a large negative voltage is applied to the gate to fill the surface with holes and decrease dark current, then dark current is reduced, but it is not easy to generate the large negative voltage
Solution Approach 1:
The patent introduces an n-type impurity layer as an intermediary structure between the p-type semiconductor substrate and the gate electrode. This intermediary layer enables the formation of a depletion region that can effectively reduce dark current without requiring large negative voltages, thus resolving the contradiction between dark current reduction and voltage generation difficulty
Solution Approach 2:
The patent changes the impurity concentration parameter by forming an n-type impurity layer with a specific concentration range (1×10^16 to 1×10^18 atoms/cm³). This parameter change allows the system to achieve effective dark current suppression through depletion region formation while operating at manageable voltage levels
2Reliability
If the difference between the depletion potential of photodiode and accumulation diode is increased to perfectly transfer charges, then charge transfer efficiency is improved, but high power supply voltage is required
Solution Approach 1:
The patent applies local quality by creating a specifically doped n-type impurity layer only in the region between the photodiode and accumulation diode. This localized modification creates a potential well that facilitates charge transfer without requiring high power supply voltages, thus resolving the contradiction between charge transfer efficiency and power consumption
Solution Approach 2:
The n-type impurity layer acts as an intermediary potential well between the photodiode and accumulation diode. This intermediary structure provides a smooth potential gradient that enables efficient charge transfer while maintaining low power supply voltage requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables perfect charge transfer and accumulation, improving sensitivity and reducing dark current, while maintaining efficient operation with lower power requirements.
Implementation Method 1
signal charges are transferred to a floating diffusion region by a potential difference between a photodiode and the floating diffusion region
Implementation Method 2
a function for transferring and accumulating electrons generated by light
Data Source
Figure 1
Figure 2(a)~2(c)
Figure 3(d)~3(e)
AI summary
A semiconductor element encompasses a base-body region (21) of p-type; a charge-generation buried region (23) of a n-type, being buried in a part of an upper portion of the base-body region (21) so as to implement a photodiode (D1) together with the base-body region (21), configured to create a first potential valley (PW1) in the base-body region (21); an accumulation region (24) of n-type, being buried in a part of the upper portion of the base-body region (21), separately from the charge-generation buried region (23), configured to create a second potential valley (PW2) deeper than the first potential valley (PW1); a transfer-gate insulation film (33) provided on a surface of the base-body region (21) between the charge-generation buried region (23) and the accumulation region (24); a transfer-gate electrode (31) provided on the transfer-gate insulation film (33), configured to control a potential of a transfer channel formed in the base-body region (21) between the charge-generation buried region (23) and the accumulation region (24); and a recessed-potential creation means configured to create a stair-like-shaped potential barrier for electronic shuttering. It is possible to achieve the perfect transfer of charges and it is possible to store a sufficient number of the accumulation charges.