Semiconductor Device Static Elimination Plug Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in scaling down while maintaining a sufficient plug grounding area to prevent arcing during manufacturing, which affects the efficiency and reliability of the devices.
Innovation Solution
The implementation of a semiconductor device design that includes a static elimination plug in the edge seal area, which is electrically connected to the substrate during manufacturing to release charges and prevent arcing, allowing for a reduced grounding area and cost-effective scaling down of semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the memory cell array is scaled down using CBA structure, then the area occupancy rate is improved, but the plug grounding area becomes insufficient leading to arcing risk
Solution Approach 1:
The patent introduces a vertical dimension by forming a plug structure that extends from the first conductive film through the first insulating film to contact the substrate. This vertical grounding path enables sufficient grounding area in the depth direction while maintaining compact planar dimensions, thus achieving both high area occupancy rate and reliable arcing prevention.
Solution Approach 2:
The plug structure is nested within the edge seal area, utilizing the existing spatial configuration. The plug is positioned between the edge seal and the element area, effectively using the vertical space within the bonding structure to provide grounding functionality without increasing the planar footprint.
2Reliability
If the plug grounding area is increased to prevent arcing, then the reliability is improved, but the device area increases reducing scaling efficiency
Solution Approach 1:
The patent resolves this contradiction by transitioning from a two-dimensional planar grounding area to a three-dimensional vertical plug structure. The plug extends in the vertical direction through the insulating film to reach the substrate, providing sufficient grounding area without increasing the planar device footprint, thus enabling continued scaling.
Solution Approach 2:
The grounding function is localized to specific regions where plugs are formed in the edge seal area. This localized approach provides grounding exactly where needed to prevent arcing during manufacturing, while leaving other areas optimized for high-density memory cell arrays, thus maintaining overall scaling efficiency.
3Area of moving object
If the plug grounding area is reduced for scaling down, then the device area is reduced, but the manufacturing cost increases due to arcing risks
Solution Approach 1:
By forming vertical plugs through the insulating film, the patent achieves sufficient grounding area in the depth direction while maintaining reduced planar dimensions. This eliminates arcing risks during manufacturing without requiring large grounding areas, thus enabling cost-effective scaling down of the device.
Solution Approach 2:
The plug structure is formed during the manufacturing process to establish grounding paths before subsequent processing steps. This preliminary grounding configuration prevents arcing during etching and other manufacturing operations, ensuring manufacturing reliability and cost-effectiveness throughout the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents arcing and allows for the scaling down of semiconductor chips while maintaining manufacturing efficiency and reliability, reducing the need for a large grounding area and lowering manufacturing costs.
Implementation Method 1
a conductive first plug provided between the first edge member and the element area in the edge area and in contact with the first insulating film
Data Source
AI summary
A semiconductor device includes a plurality of first electrode films stacked in a first direction and electrically isolated from each other; a plurality of semiconductor members extending in the first direction through the plurality of first electrode films; a first conductive film including a first surface and connected to the plurality of semiconductor members on the first surface; a first insulating film spaced from the first conductive film on a second surface of the first conductive film opposite to the first surface; a first edge member disposed in an edge area that surrounds an element area including the first electrode film, the semiconductor member, and the first conductive film; and a conductive first plug provided between the first edge member and the element area in the edge area and is in contact with the first insulating film.