Semiconductor Connecting Structure With Step-Shaped Conductive Feature
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in scaling down dimensions while maintaining quality, yield, performance, and reliability, as well as reducing complexity and cost, particularly in achieving efficient electrical signal transmission and interference reduction.
Innovation Solution
A semiconductor device with a step-shaped conductive feature is fabricated using a first connecting structure comprising a conductive layer, a porous layer, and an insulating layer, allowing for the connection of multiple semiconductor devices to enhance functionality while minimizing space, and the porous layer reduces signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional connecting structures are used to connect multiple semiconductor devices, then electrical signals can be transmitted between devices, but signal interference occurs between adjacent conductive layers
Solution Approach 1:
The patent introduces a porous layer positioned between adjacent conductive layers in the connecting structure. This porous layer acts as an interference mitigation medium that reduces signal interference between the conductive layers while maintaining electrical connectivity. The porous structure provides physical separation and electromagnetic shielding without completely blocking signal transmission.
Solution Approach 2:
The porous layer serves as an intermediary element between the conductive layers, mediating the electromagnetic interaction between them. Rather than allowing direct electromagnetic coupling that causes interference, the porous layer acts as a buffer that reduces the harmful electromagnetic fields while permitting necessary signal transmission.
2Adaptability or versatility
If multiple semiconductor devices are connected using conventional structures, then device functionality is achieved, but the device occupies larger space
Solution Approach 1:
The patent transitions from a planar connection architecture to a three-dimensional stacked architecture. Multiple semiconductor devices are connected vertically through the connecting structure with multiple conductive layers arranged in different vertical levels. This dimensional change allows more devices to be interconnected within a smaller footprint area by utilizing the vertical dimension for signal routing and device stacking.
3Productivity
If dimension scaling is pursued to improve computing ability, then device density increases, but manufacturing complexity and quality maintenance become more difficult
Solution Approach 1:
The connecting structure is segmented into multiple distinct functional layers: first and second conductive layers for signal transmission, a porous layer for interference reduction, and insulating layers for electrical isolation. This segmentation allows each layer to be optimized independently for its specific function, simplifying the manufacturing process for each layer while achieving complex overall functionality in the scaled-down device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables more sophisticated functions in a compact form, reduces costs, and improves signal transmission by alleviating interference effects between electrical signals.
Implementation Method 1
a first porous layer positioned between the two first conductive layers
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a first connecting structure, and a second semiconductor structure positioned on the first connecting structure. The first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. The second semiconductor structure is positioned on the first connecting structure and includes two second conductive features positioned on the two first conductive layers. The first conductive layer has a first width, the second conductive feature has a second width greater than the first width, and the different width forms a step-shaped cross-sectional profile near an interface of the first conductive layer and the second conductive feature.