Semiconductor Step Structure Etching for Higher 3D Memory Density
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Solution Overview
Problem
The reduction of semiconductor chip dimensions is limited by photolithography steppers, and three-dimensional memory structures require extensive step formation, leading to increased step area and decreased storage density due to overall etching and poor structural stability.
Innovation Solution
A manufacturing method involving a substrate with a stacked structure, a hard mask layer with etched windows, and a photoresist layer that is trimmed multiple times to etch the structure, forming steps that reduce the occupied area and improve integration, thereby enhancing storage density without damaging the support frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If overall etching is used to form steps in three-dimensional memory, then connections between different layers can be implemented, but the area occupied by steps increases and storage density decreases
Solution Approach 1:
The patent applies segmentation by dividing the etching process into multiple stages: first forming a preliminary step structure, then performing selective etching on specific regions to create final contact holes. This segmented approach allows steps to be formed only where needed rather than across the entire structure, reducing the total area occupied by steps while maintaining layer connectivity.
Solution Approach 2:
The patent implements local quality by applying different etching treatments to different regions of the three-dimensional memory structure. Specifically, selective etching is performed on certain areas to form contact holes while leaving other areas intact, allowing the step structure to provide local connections without occupying excessive area throughout the entire device.
2Quantity of substance
If more layers are added to increase storage density, then storage capacity improves, but the region occupied by steps increases and core region area decreases
Solution Approach 1:
The patent segments the contact hole formation process into preliminary step formation followed by selective etching. This allows the structure to accommodate more layers without proportionally increasing step area, as the selective etching approach creates connections only where required rather than forming steps across the entire expanded structure.
Solution Approach 2:
The patent utilizes vertical dimensionality by forming stepped structures that extend in the vertical direction to accommodate multiple layers. This dimensional approach allows storage density to increase through vertical stacking while the selective etching process ensures that horizontal area consumption by steps is minimized.
3Reliability
If conventional etching methods are used, then steps can be formed for layer connections, but structural stability deteriorates
Solution Approach 1:
The patent segments the etching process into preliminary and selective stages, where the preliminary step formation creates a stable framework structure first. This framework provides structural support before selective etching creates final connections, ensuring that structural stability is maintained throughout the process while still achieving layer connectivity.
Solution Approach 2:
The patent applies preliminary action by forming a preliminary step structure before performing selective etching. This preliminary structure provides a stable framework that maintains structural integrity during subsequent processing steps, preventing structural deterioration while enabling the formation of stable layer connections.
Data Source
AI summary
The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate, and forming a stacked structure on the substrate; forming a hard mask layer on the stacked structure, where the hard mask layer includes a first etched window, and the first etched window exposes part of a top surface of the stacked structure; forming a photoresist layer, where the photoresist layer covers the first etched window; and trimming the photoresist layer for a plurality of times, after each trimming of the photoresist layer, etching the stacked structure according to a trimmed photoresist layer, and forming a plurality of steps in the stacked structure along a direction away from the substrate.