Semiconductor Device With Step Gate Dielectric Structure
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Solution Overview
Problem
Conventional high voltage LDMOS devices face challenges in reducing on-resistance while maintaining high breakdown voltage, as increasing device size to withstand high voltage leads to increased on-resistance.
Innovation Solution
The semiconductor device incorporates a substrate with a shallow trench isolation structure, a gate dielectric layer, and a step gate dielectric structure with a thickness greater than the gate dielectric layer but less than the isolation structure, replacing the conventional field oxide with a local oxidation of silicon (LOCOS) in the field plate region to shorten the current path from drain to source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the device size is increased to withstand high breakdown voltage, then the breakdown voltage is improved, but the on-resistance is increased
Solution Approach 1:
The patent applies local quality by creating a step gate dielectric structure with different thicknesses in different regions. The gate dielectric layer has a first thickness in the field plate region and a second thickness in other regions, allowing localized optimization of electrical characteristics to reduce on-resistance while maintaining high breakdown voltage capability
Solution Approach 2:
The patent introduces a vertical dimension variation through the step gate dielectric structure, where the dielectric thickness changes in the vertical direction across different horizontal regions. This dimensional change enables simultaneous achievement of low on-resistance (through thinner dielectric in active regions) and high breakdown voltage (through thicker dielectric in field plate regions)
Data Source
AI summary
A semiconductor device is disclosed. An isolation structure is formed in a substrate to define an active region of the substrate, wherein the active region has a field plate region. A gate dielectric layer is formed on the substrate outside of the field plate region. A step gate dielectric structure is formed on the substrate corresponding to the field plate region, wherein the step gate dielectric structure has a thickness greater than that of the gate dielectric layer and less than that of the isolation structure. A method for forming a semiconductor device is also disclosed.