Semiconductor Device Step-Like Source Drain Epitaxial Areas
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Solution Overview
Problem
In semiconductor devices with gate lengths less than or equal to 90 nm, the leak current increases due to miniaturization, hindering the reduction of power consumption and enhancement of current driving capability, and existing strained silicon technologies face challenges in applying sufficient compressive stress to the channel area without increasing parasitic resistance.
Innovation Solution
A method of manufacturing semiconductor devices with step-like source/drain epitaxial areas, where a dopant implantation area is formed, recesses are etched, and a semiconductor material is grown in these recesses to create stressor regions that apply compressive or tensile stress to the channel area, reducing parasitic resistance and enhancing mobility without increasing manufacturing complexity or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced to increase integration density, then the integration density and driving speed are improved, but the leak current increases
Solution Approach 1:
The source/drain structure is segmented into multiple regions with different materials and doping concentrations. The channel region is separated from the source/drain extension by a junction, creating distinct functional zones that allow independent optimization of each region's properties to reduce leak current while maintaining high integration density
Solution Approach 2:
Different regions of the semiconductor structure are assigned different material compositions and doping levels. The source/drain extension has higher doping concentration than the channel, and specific regions use different semiconductor materials (e.g., SiGe vs Si) to create local variations in electrical properties that suppress leak current at the miniaturized gate length
2Loss of energy
If the leak current is reduced to a predetermined value, then power consumption is reduced, but the current driving capability becomes difficult to enhance
Solution Approach 1:
The source/drain extension region is doped at a higher concentration than the channel region, creating a localized high-conductivity path that reduces parasitic resistance and improves current driving capability without increasing the leak current through the channel. This local variation in doping concentration allows simultaneous optimization of both power consumption and driving capability
Solution Approach 2:
The semiconductor structure uses composite materials with different properties in different regions. The source/drain extension uses highly doped semiconductor material while the channel uses lightly doped or undoped material, creating a composite structure that provides both low resistance for current driving and high barrier for leak current suppression
3Power
If a dopant implantation area is formed and recesses are etched to create source/drain epitaxial areas, then hole or electron mobility is increased and parasitic resistance is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
Multiple manufacturing steps are merged into an integrated process flow. The dopant implantation, recess formation, and selective epitaxial growth are combined in a sequence that uses the gate electrode and sidewalls as self-aligned masks, eliminating the need for separate masking and alignment steps that would increase process complexity
Solution Approach 2:
The gate electrode and sidewalls serve as self-aligned masks for the dopant implantation and epitaxial growth processes. The structure itself provides the patterning function, eliminating the need for additional photolithography and masking steps, thereby reducing manufacturing complexity while achieving the desired source/drain epitaxial areas
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases hole or electron mobility while reducing parasitic resistance, preventing roll-off and short channel effects, thereby enhancing transistor performance without increasing manufacturing complexity or cost.
Implementation Method 1
forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask
Implementation Method 2
forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess
Implementation Method 3
forming sidewalls on the gate electrode
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess.