Semiconductor Package Step-Trench Structure for Low-Chip Wafer Cutting

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Solution Overview

Problem

Current semiconductor manufacturing processes face challenges in efficiently producing reliable semiconductor devices with complex packaging structures, particularly in the wafer-level packaging process, where precise cutting and bonding techniques are required to minimize damage and enhance bonding strength.

Innovation Solution

The process involves a method of wafer-level packaging that includes forming trenches in a wafer substrate with a step-form profile, allowing for precise cutting and bonding of semiconductor devices, and using insulating materials to enhance bonding strength and reliability, while minimizing chipping and ensuring heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If precise cutting techniques are used to form trenches in wafer substrate, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvetrench cutting precisionVSAvoidpackaging structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The wafer substrate is divided into multiple trenches that segment the packaging structure into distinct regions. Each trench acts as an independent barrier, allowing precise control over material placement and bonding interfaces while maintaining overall structural integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the packaging structure are assigned different properties: trenches provide mechanical separation and insulation, while bonding pads provide electrical connectivity. This local differentiation allows each region to be optimized for its specific function, improving overall manufacturing precision without uniformly increasing complexity.

Inventive Principle:
Principle #3Local quality

2Reliability

If bonding strength is enhanced through advanced bonding techniques, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvebonding strengthVSAvoidbonding process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Bonding pads are pre-formed on the wafer substrate before final assembly. This preliminary action ensures that bonding surfaces are prepared in advance with correct positioning and material properties, enabling strong bonding during final assembly without requiring complex real-time adjustment mechanisms.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Bonding pads serve as intermediary elements between the wafer substrate and external connections. These pads concentrate and distribute bonding forces, enabling reliable electrical and mechanical connections while simplifying the overall bonding process by providing dedicated bonding interfaces.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If chipping is minimized through optimized cutting processes, then manufacturing precision is improved, but production time increases

Engineering Contradiction:
Improvechip damage reductionVSAvoidcutting process time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The packaging structure is designed with trenches and bonding pads that provide mechanical support and stress distribution before cutting operations. This beforehand cushioning prevents chipping during the cutting process by reducing stress concentration at cut edges, allowing faster cutting speeds without increasing damage rates.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11901256B2Semiconductor device, semiconductor package, and methods of manufacturing the same
Publication Date: 2024.02.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11901256B2 patent drawing
  • US11901256B2 patent drawing
  • US11901256B2 patent drawing

AI summary

A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.