Semiconductor Device With Stepped Diffusion Barrier
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Solution Overview
Problem
Thermo-mechanical stresses in integrated circuits due to material mismatches between copper re-distribution layers (RDL) and passivation layers, such as silicon nitride, lead to reliability issues during wire bonding and packaging processes in BCD technology-based semiconductor devices.
Innovation Solution
A semiconductor device design featuring a diffusion barrier layer with a step structure that decouples the capping layer from the passivation surface, eliminating the 'triple point' of contact between the barrier, capping, and passivation layers, and incorporating a hollow recess area to reduce mechanical stress on the underlying dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a copper re-distribution layer (RDL) is deposited over a passivation layer (SiN) in BCD technology, then thick metal interconnections are achieved for power electronics and logical control, but thermo-mechanical stresses arise due to material mismatch between different layers
Solution Approach 1:
The barrier layer is segmented into two distinct portions: a first portion in direct contact with the passivation layer and a second portion extending upward to contact the capping layer. This segmentation allows each portion to independently manage different stress regimes, with the first portion providing diffusion barrier function and the second portion providing mechanical stress relief, thereby resolving the contradiction between achieving thick metal interconnections and reducing thermo-mechanical stress.
Solution Approach 2:
The barrier layer acts as an intermediary structure between the passivation layer and the capping layer. By introducing this intermediate barrier layer with a stepped configuration, the patent mediates the thermo-mechanical stress transfer between the mismatched copper RDL and SiN passivation layer, preventing direct stress transmission while maintaining the necessary electrical and structural functions.
2Reliability
If a triple point of contact exists between the barrier layer, capping layer, and passivation layer, then complete coverage and protection are achieved, but high mechanical stress concentrates at this intersection point
Solution Approach 1:
The invention extracts or removes the problematic triple point of contact by extending the barrier layer upward to contact the capping layer before the capping layer can contact the passivation layer. This extraction eliminates the high-stress concentration zone while maintaining complete protection coverage through the extended barrier layer structure that provides continuous diffusion barrier and mechanical support.
3Ease of manufacture
If the barrier layer is deposited as a single continuous layer, then manufacturing simplicity is maintained, but it cannot simultaneously provide diffusion barrier function and mechanical stress relief
Solution Approach 1:
The barrier layer is designed with local quality variations through its stepped configuration. The first portion (in contact with passivation layer) and the second portion (extending upward) have different functional requirements and structural characteristics. This local differentiation allows the single barrier layer to simultaneously provide diffusion barrier function at the interface with the passivation layer and mechanical stress relief where it contacts the capping layer, achieving multiple functions without requiring multiple separate deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces mechanical stress on the passivation layer, enhancing the reliability of the semiconductor device by eliminating the high-stress triple point and improving thermal budget resilience.
Implementation Method 1
a diffusion barrier layer separating the peripheral portion of the interconnection metallization from the passivation layer
Implementation Method 2
thermo-mechanical stresses in integrated circuits due to material mismatches between copper re-distribution layers (RDL) and passivation layers
Data Source
AI summary
A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.


