Semiconductor Device Stepped Conductive Patterns Contact Plug Reliability
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Solution Overview
Problem
In semiconductor devices, the edge portions of stacked conductive patterns often have a step shape, leading to challenges in forming contact plugs without bridge failures or defects, particularly due to the thickness and positioning of pad patterns.
Innovation Solution
The semiconductor device design includes conductive patterns with step portions, insulation patterns, sidewall insulation patterns, and upper pad patterns made of polysilicon, with an insulating interlayer covering these features and contact plugs passing through to contact the upper pad patterns, ensuring proper alignment and reduced defect rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed on stepped conductive patterns, then vertical integration is achieved, but bridge failures and defects occur between neighboring pad patterns
Solution Approach 1:
An insulating interlayer is introduced as an intermediary between the stepped conductive patterns and the contact plugs. This insulating interlayer covers the conductive patterns and provides a planarized surface, preventing direct contact between neighboring pad patterns while allowing vertical connection through contact plugs. The insulating interlayer acts as a mediator that resolves the conflict between achieving vertical integration and preventing bridge failures.
2Reliability
If pad patterns are made thicker to ensure contact plug formation, then contact reliability improves, but bridge failures between neighboring pads increase
Solution Approach 1:
The structure is segmented into distinct functional layers: conductive patterns for electrical connection, insulating patterns for isolation, and an insulating interlayer for planarization and protection. By segmenting the structure, the pad patterns can maintain sufficient thickness for reliable contact while the insulating interlayer prevents bridge failures between neighboring pads, allowing each layer to perform its specific function without compromising the others.
3Productivity
If stepped conductive patterns are used for vertical stacking, then device integration density increases, but process defects occur during contact plug formation
Solution Approach 1:
The insulating interlayer is formed in advance before contact plug formation, creating a planarized surface that facilitates precise contact plug alignment. This preliminary action of planarization ensures that subsequent contact plug formation can be performed with high precision, even on stepped conductive patterns, thereby maintaining both high integration density and manufacturing precision.
Data Source
AI summary
A semiconductor device a substrate; conductive patterns on the substrate, the conductive patterns being spaced apart from each other in a vertical direction perpendicular to a surface of the substrate, and an edge of the conductive patterns including a step portion such that an end of one conductive pattern is not overlapped in the vertical direction with conductive patterns positioned thereover; insulation patterns between the conductive patterns; sidewall insulation patterns on the sidewalls of the conductive patterns to cover sidewalls of the conductive patterns; upper pad patterns on upper surfaces of the step portion of the conductive patterns and upper surfaces of a portion of the sidewall insulation patterns; an insulating interlayer covering the conductive patterns, the insulation patterns, the sidewall insulation patterns, and the upper pad patterns; and contact plugs passing through the insulating interlayer, the contact plugs contacting the upper pad patterns, respectively.