Semiconductor Device With Stepped Edge And Rear Terminals
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Solution Overview
Problem
Semiconductor devices face degradation in high frequency characteristics due to long bonding wires and increased parasitic capacitance when external terminals are connected to the base, leading to larger package sizes and compromised performance.
Innovation Solution
A semiconductor device design featuring a base with stepped edge portions and strategically positioned terminals, where the semiconductor element and terminals are connected by a conductive member, reducing wire length and parasitic capacitance, and using resin material for sealing, which helps in suppressing the degradation of high frequency characteristics and package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to connect semiconductor element to base leads, then electrical connection is achieved, but high frequency characteristics are degraded due to long wire length
Solution Approach 1:
The patent transitions from planar connection to three-dimensional connection by having the conductive member extend from the front surface through the base to the rear surface. This vertical dimensionality change allows the conductive member to connect the semiconductor element to external terminals with significantly reduced length, improving high frequency characteristics.
Solution Approach 2:
Instead of connecting terminals to the front surface of the base (conventional approach), the patent inverts the connection approach by providing external terminals on the rear surface of the base. This inversion allows the conductive member to pass through the base thickness, shortening the connection path and reducing parasitic effects.
2Reliability
If external terminals are connected to the base, then electrical connection is achieved, but parasitic capacitance increases leading to degraded high frequency characteristics
Solution Approach 1:
The patent extracts the terminal connection function from the front surface of the base and relocates it to the rear surface. By taking out the terminals from their conventional position and placing them on the rear surface, the patent reduces the overlapping area between terminals and the semiconductor element, thereby reducing parasitic capacitance.
Solution Approach 2:
The patent moves terminal connections from the front surface plane to the rear surface plane, utilizing the thickness dimension of the base. This dimensional transition reduces the proximity between terminals and the semiconductor element, minimizing capacitive coupling and parasitic effects.
3Volume of moving object
If terminals are positioned close to the base, then package size is reduced, but parasitic capacitance between terminal and base increases
Solution Approach 1:
The patent resolves this contradiction by utilizing the thickness dimension of the base. Terminals are positioned on the rear surface, vertically separated from the semiconductor element on the front surface. This dimensional separation allows compact packaging while maintaining small parasitic capacitance through increased vertical spacing.
Solution Approach 2:
Instead of placing terminals on the front surface near the semiconductor element, the patent inverts the arrangement by placing terminals on the rear surface. This inversion enables compact package design while the base thickness provides natural spacing that minimizes parasitic capacitance.
4Reliability
If bonding wires are used for connection, then electrical connection is achieved, but device complexity increases
Solution Approach 1:
The patent merges the connection function into the base structure itself. The base serves dual purposes: as the mounting substrate for the semiconductor element and as the structural medium containing the conductive member that provides electrical connection. This integration eliminates separate bonding wire components and simplifies the overall device structure.
Solution Approach 2:
The patent extracts the bonding wire function and replaces it with a conductive member embedded in the base. By taking out the external bonding wire and integrating the connection path within the base structure, the patent simplifies the device by eliminating fragile wire bonds and reducing assembly complexity.
Data Source
AI summary
A semiconductor device includes a base having a first surface on which the semiconductor element is mounted and a second surface opposite to the first surface, a first edge portion having a step from the first surface toward the second surface in a first region of a peripheral edge of the base, a first terminal that is arranged at a position facing the first edge portion when viewed from a thickness direction of the base, a conductive member for electrically connecting the semiconductor element and the first terminal to each other, and a resin material for sealing a part of the base, the semiconductor element, and a part of the first terminal.