Semiconductor Device With Stepped Oxide Layer For Low Rsp
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Solution Overview
Problem
High voltage semiconductor devices face challenges in minimizing specific on-resistance (Rsp) and gate charge (Qg), leading to increased conduction loss and Figure of Merit (FOM) values, which are critical for efficient operation and power management.
Innovation Solution
The semiconductor device design incorporates a deep well region, second conductivity type drift and body regions, and a stepped oxide layer structure, replacing traditional trench isolation with thicker gate insulating layers to reduce resistance and extend the drift region, thereby minimizing accumulation region length and gate charge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the drift region is heavily doped to reduce resistance, then conduction loss decreases, but breakdown voltage is greatly lowered
Solution Approach 1:
The patent applies different doping concentrations to different regions: the drift region is heavily doped to reduce conduction loss, while the body region maintains lower doping to preserve breakdown voltage. This spatial differentiation of doping quality allows simultaneous optimization of both conduction and blocking characteristics.
Solution Approach 2:
The invention transitions from a planar structure to a three-dimensional stacked structure with multiple regions (drift region, body region, accumulation region) arranged in vertical layers. This dimensional change enables independent optimization of each region's properties without compromising overall device performance.
2Reliability
If RESURF technology is used to extend depletion region and increase breakdown voltage, then high voltage capability is achieved, but accumulation region length increases and gate charge Qg increases
Solution Approach 1:
The device is segmented into distinct functional regions: drift region for voltage blocking, body region for channel formation, and accumulation region for charge storage. This segmentation allows each region to be optimized independently, reducing the overall gate charge while maintaining high breakdown voltage through the drift region's extended depletion layer.
3Reliability
If accumulation region length is increased to improve voltage blocking, then breakdown voltage increases, but Figure of Merit Ron×Qg increases
Solution Approach 1:
The patent optimizes the doping concentration parameter in the accumulation region to achieve the right balance: sufficient doping to maintain voltage blocking capability while limiting the accumulation region length to reduce gate charge. This parameter optimization enables low Figure of Merit while preserving high breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces Rsp by approximately 50% and Qg by 60%, improving breakdown voltage and power efficiency, making it suitable for high frequency applications.
Implementation Method 1
A strength of an electric field vertically applied on a substrate is greatly reduced
Implementation Method 2
A depletion region is extended to an entire n-type epitaxial layer by growing a thick n-type epitaxial layer on a p-type substrate
Data Source
AI summary
The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.