3D Semiconductor Memory Stepped Stack for Stable Word Line Scaling

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Solution Overview

Problem

The stability of manufacturing processes and structural stability in three-dimensional semiconductor memory devices deteriorate as the number of stacked word lines increases, leading to challenges in maintaining the integrity and efficiency of the device.

Innovation Solution

A semiconductor memory device design featuring a first stack with lower conductive patterns forming a lower stepped structure, support pillars with insulating layers, and a second stack with upper conductive patterns forming an upper stepped structure that does not overlap with the lower stepped structure or support pillars, along with a channel structure passing through both stacks, is implemented. This design includes forming sacrificial pillars, etching to create stepped structures, and filling with insulating layers to enhance stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of stacked word lines is increased to increase the degree of integration, then the device capacity is improved, but the manufacturing process stability and structural stability deteriorate

Engineering Contradiction:
Improvenumber of stacked word linesVSAvoidmanufacturing process stability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The gate electrode stack is divided into multiple segments with different widths at different heights, creating a stepped structure. This segmentation reduces the overall footprint and improves manufacturing stability by breaking down the complex stacking process into manageable sections, allowing for better control of each individual layer during fabrication.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a two-dimensional planar arrangement to a three-dimensional stepped structure by varying the width of conductive patterns at different heights. This dimensional change allows increased integration density vertically while maintaining manufacturing stability through the stepped configuration that provides better structural support and easier fabrication control.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the number of stacked word lines is increased to increase the degree of integration, then the device capacity is improved, but the structural stability deteriorates

Engineering Contradiction:
Improvenumber of stacked word linesVSAvoidstructural stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The gate electrode stack is divided into multiple segments with different widths at different heights, creating a stepped structure. This segmentation reduces the overall footprint and improves manufacturing stability by breaking down the complex stacking process into manageable sections, allowing for better control of each individual layer during fabrication.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs asymmetric conductive patterns where the width of each conductive layer varies at different heights of the stack. This asymmetric stepped design optimizes structural stability by providing a broader base that tapers upward, distributing mechanical stress more effectively and enhancing the overall structural integrity of the high-density stacked configuration.

Inventive Principle:
Principle #4Asymmetry

3Quantity of substance

If complex stacked structures are formed to increase integration, then the device capacity is improved, but the manufacturing process complexity increases

Engineering Contradiction:
Improvedegree of integrationVSAvoidmanufacturing process complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The gate electrode stack is divided into multiple segments with different widths at different heights, creating a stepped structure. This segmentation reduces the overall footprint and improves manufacturing stability by breaking down the complex stacking process into manageable sections, allowing for better control of each individual layer during fabrication.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent forms the stepped structure of conductive patterns before completing the full stacking process. This preliminary action establishes a stable framework that guides subsequent fabrication steps, making the overall manufacturing process more manageable by providing reference structures early in the process sequence.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11751384B2Semiconductor memory device and manufacturing method of the semiconductor memory device
Publication Date: 2023.09.05 SK HYNIX INC
  • US11751384B2 patent drawing
  • US11751384B2 patent drawing
  • US11751384B2 patent drawing

AI summary

A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.