Semiconductor Stepped Via Structure with Air-Gap Regions

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Solution Overview

Problem

High integration and close proximity of wiring lines in semiconductor devices lead to increased interference, resulting in lower signal transmission speeds due to the difficulty in etching copper wiring lines and the resulting narrow distances between them.

Innovation Solution

A semiconductor device design featuring a stepped structure with misaligned via and wiring sidewalls, air-gap regions, and different insulation layers to reduce parasitic capacitance and enhance signal transmission speed, including a damaged region with altered carbon concentration in the interlayer insulation layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If wiring lines are placed closer together to achieve high integration, then device density is improved, but signal transmission speed deteriorates due to increased interference and parasitic capacitance

Engineering Contradiction:
Improvedevice densityVSAvoidsignal transmission speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

An air-gap region is introduced as an intermediary between adjacent wiring lines. This air-gap acts as a mediator that reduces parasitic capacitance between the wiring lines, thereby maintaining signal transmission speed even when lines are placed closer together for high integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The air-gap region is selectively formed only in specific locations between wiring lines where parasitic capacitance is problematic. This local modification allows the wiring lines to be placed closer together in other areas, achieving high integration while maintaining signal transmission speed in critical regions.

Inventive Principle:
Principle #3Local quality

2Reliability

If copper is used for wiring lines to achieve low resistivity and low cost, then electrical performance is improved, but manufacturing complexity increases due to etching difficulties

Engineering Contradiction:
Improveelectrical performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A liner layer is introduced as an intermediary between the copper wiring line and the surrounding insulation layer. This liner acts as a mediator that protects the copper from oxidation and facilitates the etching process, enabling copper to be used for its excellent electrical properties without compromising manufacturability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If air-gap regions are formed to reduce parasitic capacitance and improve signal transmission speed, then electrical performance is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvesignal transmission speedVSAvoidair-gap formation precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The air-gap region is formed through a self-aligned process where the air-gap is created as a byproduct of the existing manufacturing steps rather than requiring a separate precision alignment step. The etching process that removes sacrificial layers automatically creates the air-gap regions in the correct positions, eliminating the need for additional precision alignment.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively reduces parasitic capacitance between adjacent wiring lines, increasing signal transmission speed by utilizing air-gap regions and altered carbon concentration in the damaged region, thereby improving the performance of high integration semiconductor devices.

Implementation Method 1

reduces parasitic capacitance between adjacent wiring lines, increasing signal transmission speed

Methodology Applied
Scientific EffectParasitic capacitance: Capacitance

Implementation Method 2

A carbon concentration in the damaged region may be lower than a carbon concentration in the interlayer insulation layer and be higher than a carbon concentration in the second insulation layer

Methodology Applied
Scientific EffectCarbon concentration gradient: Diffusion

Data Source

PatentUS10410916B2Semiconductor device
Publication Date: 2019.09.10 SAMSUNG ELECTRONICS CO LTD
  • US10410916B2 patent drawing
  • US10410916B2 patent drawing
  • US10410916B2 patent drawing

AI summary

A semiconductor device includes an interlayer insulation layer on a semiconductor substrate, a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure. The semiconductor device includes a first air-gap region between the interlayer insulation layer and the via plug, and a second air-gap region between the interlayer insulation layer and the wiring line. The first air-gap region and the second air-gap region are not vertically overlapped with each other.