Semiconductor Isolation Structure for Coplanar STI Active Areas
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Solution Overview
Problem
Conventional methods for semiconductor devices, particularly in dynamic-random access memory (DRAM), result in rounding of active areas, leading to reduced contact area and deteriorated electrical performance due to shallow trench isolation (STI) loss.
Innovation Solution
A method involving a semiconductor structure with a silicon substrate and oxide material-filled trenches, where a pad oxide layer is formed on top to ensure the top surface of the oxide material and island structures are coplanar, reducing oxide material loss and rounding issues, and using a nitride filling material to completely fill trenches, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If wet cleaning time is decreased to mitigate rounding issue, then active area rounding is reduced, but STI loss issue remains unsolved
Solution Approach 1:
A pad oxide layer is formed on the oxide material surface before subsequent processing steps. This preliminary protective layer prevents oxide material loss during wet cleaning and other processing, eliminating STI loss while allowing adequate cleaning time to also reduce active area rounding.
Solution Approach 2:
The pad oxide layer acts as an intermediary protective layer between the oxide material and the wet cleaning process. It absorbs the harmful effect of wet cleaning on the oxide material, preventing direct contact and loss of oxide material while still allowing the cleaning process to reduce rounding of active areas.
2Ease of manufacture
If conventional manufacturing methods are used, then manufacturing process is simple, but electrical performance deteriorates due to rounding and reduced contact area
Solution Approach 1:
The pad oxide layer is formed as a preliminary protective layer before subsequent processing steps. This simple additional step prevents oxide material loss and maintains active area shape, thereby improving electrical performance without significantly complicating the manufacturing process.
Solution Approach 2:
The method introduces a new parameter (pad oxide layer thickness) that can be controlled to optimize both protection against oxide loss and maintenance of active area shape. By adjusting this parameter, electrical performance is improved while keeping the process relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances electrical performance by preventing oxide material loss and maintaining the integrity of island structures, ensuring improved contact areas and reduced resistivity.
Implementation Method 1
forming the pad oxide layer is performed by an ion implantation process
Implementation Method 2
removing the pad oxide layer is performed by a wet etch process
Implementation Method 3
removing the pad oxide layer is performed by using hydrofluoric acid
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a semiconductor structure, in which the semiconductor structure comprises a silicon substrate having a plurality of trenches and an oxide material filled in the trenches and covering the silicon substrate, and the trenches define a plurality of island structures; forming a pad oxide layer on a top portion of the oxide material, in which the pad oxide layer is located over the silicon substrate; and removing the pad oxide layer, so that a top surface of the oxide material and a top surface of the island structures are coplanar.