Semiconductor Device Fabrication Using Shallow Trench Isolation and Dummy Gate Replacement
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in creating efficient and compact transistor structures that accommodate both low-voltage and high-voltage operations within the same device, while maintaining compatibility with existing fabrication processes and reducing fabrication costs.
Innovation Solution
The semiconductor device employs a shallow trench isolation structure and a dummy gate replacement technique, where a gate doped region serves as a second gate structure, and the semiconductor layer includes isolation doped regions of different conductivity types, allowing for the formation of a channel layer and source/drain layers using materials like polycrystalline silicon or indium gallium zinc oxide, with the option to use a silicon substrate or epitaxial layer, enabling the fabrication of both general and high-voltage transistors in a compatible process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional transistor structures are used, then fabrication processes are simple, but the device cannot accommodate both low-voltage and high-voltage operations efficiently
Solution Approach 1:
The device is segmented into two distinct transistor types: a first transistor with a gate structure for low-voltage operation and a second transistor with a gate doped region for high-voltage operation. This segmentation allows each transistor to be optimized for its specific voltage range while sharing the same semiconductor layer and fabrication process, thereby improving adaptability without excessive complexity
Solution Approach 2:
The invention uses a universal fabrication process that can create both low-voltage and high-voltage transistors from the same semiconductor layer. The shallow trench isolation structure and dummy gate replacement technique serve multiple functions: they define device regions, enable selective doping, and facilitate the formation of both transistor types using identical process steps, achieving multi-functionality in the fabrication approach
2Productivity
If advanced transistor structures are implemented, then voltage operation efficiency improves, but fabrication complexity and cost increase
Solution Approach 1:
A dummy gate structure is formed preliminarily across both device regions before the actual gate structures are created. This preliminary action establishes a reference framework that guides subsequent selective removal and doping processes, enabling efficient formation of both transistor types without requiring complex alignment steps or multiple lithography processes
Solution Approach 2:
The fabrication process uses a copied approach where the same shallow trench isolation structure and dummy gate replacement technique are applied to both the first and second device regions. This copying of proven fabrication steps across different device regions maintains process simplicity while enabling the creation of advanced transistor structures for both voltage ranges
3Reliability
If isolation structures are added to separate device regions, then device performance improves, but fabrication steps increase
Solution Approach 1:
The shallow trench isolation structure is merged with the device region definition process. The same etching and filling steps that create the isolation structures also define the boundaries of the first and second device regions. This merging eliminates the need for separate isolation fabrication steps, maintaining ease of manufacture while achieving reliable device isolation and performance
Data Source
AI summary
Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.