Semiconductor Package Stiffener for Warpage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages with multiple chips experience warpage due to differences in coefficients of thermal expansion, leading to increased bowing and reduced co-planarity, which complicates integration with PCBs and affects performance.
Innovation Solution
Incorporating a stiffener with a plate shape between semiconductor chips, connected using an adhesive layer, to cover the space between them and reduce thermal expansion mismatches, thereby minimizing warpage and enhancing co-planarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are mounted on a single interposer or package substrate, then the semiconductor package achieves high performance, high speed, and small size, but warpage occurs due to difference in coefficients of thermal expansion between elements
Solution Approach 1:
The patent applies local quality by positioning stiffeners at specific locations between adjacent semiconductor chips where thermal expansion differences cause the most significant warpage. The stiffeners are strategically placed in regions with high thermal stress concentration, providing localized reinforcement rather than uniform support across the entire package substrate.
Solution Approach 2:
The patent employs composite materials by combining stiffener elements with the package substrate and semiconductor chips. The stiffeners are made from materials having intermediate coefficients of thermal expansion between the substrate and chips, creating a composite structure that bridges the thermal expansion mismatch and reduces overall package warpage.
2Productivity
If multiple semiconductor chips are mounted on a single interposer or package substrate, then the semiconductor package achieves high performance, high speed, and small size, but the magnitude of warpage increases
Solution Approach 1:
The patent applies local quality by positioning stiffeners at specific locations between adjacent semiconductor chips where thermal expansion differences cause the most significant warpage. The stiffeners are strategically placed in regions with high thermal stress concentration, providing localized reinforcement rather than uniform support across the entire package substrate.
Solution Approach 2:
The patent employs the anti-weight principle by using stiffeners as counteracting elements that provide mechanical support opposing the warpage forces. The stiffeners act as structural counterweights that balance the thermal expansion-induced bending moments, reducing the net warpage magnitude of the multi-chip package.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stiffener effectively reduces warpage and improves co-planarity, ensuring better integration with PCBs and maintaining performance specifications while being lightweight and compliant with industry standards.
Implementation Method 1
connected using an adhesive layer
Implementation Method 2
A warpage in a semiconductor package may be caused by a difference in coefficients of thermal expansion between elements constituting the semiconductor package
Data Source
AI summary
A semiconductor package includes a first substrate having a first surface and a second surface opposite to the first surface, a first semiconductor chip on the first surface of the first substrate, a second semiconductor chip on the first surface of the first, a stiffener on the first semiconductor chip and the second semiconductor chip, and an encapsulant on the first surface of the first substrate. The first substrate includes a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof. The first semiconductor chip is connected to a first group of first pads of the plurality of first pads. The second semiconductor chip is connected to a second group of first pads of the plurality of first pads. The stiffener covers a space between the first semiconductor chip and the second semiconductor chip. The encapsulant covers at least a sidewall of each of the first and second semiconductor chips and the stiffener.