Semiconductor Layout Stitching With Alignment Regions for Overlay Accuracy
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Solution Overview
Problem
The increasing complexity and size of integrated circuits (ICs) require advanced lithography techniques to pattern semiconductor substrates efficiently, as the area of the semiconductor structure often exceeds the size that can be covered by a single mask, necessitating the stitching of multiple masks together while maintaining precise alignment and overlay accuracy.
Innovation Solution
A lithography system and process that uses multiple masks with stitching regions and alignment marks to expose and pattern semiconductor substrates, allowing for the formation of larger semiconductor structures by overlapping and aligning features across multiple masks, enabling the creation of circuit features and alignment regions for precise overlay measurement and process control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple masks are stitched together to create larger semiconductor structures, then the area size of the semiconductor structure is increased, but the alignment precision and overlay accuracy deteriorate
Solution Approach 1:
The patent divides the large semiconductor structure into multiple smaller regions, each exposed by a separate mask. The substrate is segmented into first and second regions exposed by first and second masks respectively, with stitching regions where they overlap. This segmentation allows each mask to maintain its own alignment references independently while contributing to the overall large structure.
Solution Approach 2:
The patent introduces alignment marks as intermediary elements that facilitate precise alignment between multiple masks. These alignment marks are formed in the stitching regions and serve as reference points for overlay measurement and adjustment, enabling accurate registration of features from different masks without direct mechanical alignment.
2Adaptability or versatility
If the complexity and integration density of integrated circuits are increased, then the functionality and processing capability are improved, but the area size of the IC is increased
Solution Approach 1:
The patent extends the fabrication capability from two-dimensional single-mask exposure to a multi-dimensional approach using multiple masks that can be stitched together. This allows the creation of semiconductor structures with area sizes exceeding the capabilities of any single mask, effectively adding a dimensional aspect to the patterning process capacity.
Data Source
AI summary
Semiconductor structures are provided. A semiconductor structure includes a plurality of product regions over a semiconductor substrate, a plurality of alignment regions over the semiconductor substrate, and a plurality of first features formed in a material layer over the semiconductor substrate. Each of the alignment regions is surrounded by four of the product regions of a group, and each of the first features extends across two adjacent product regions in the group. The product regions are disposed in rows and columns of a first array, and the alignment regions are disposed in rows and columns of a second array, and the first and second arrays have a same center point.