Semiconductor Stitching Layout With Overlapping Masks for Large Dies
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Solution Overview
Problem
Current semiconductor manufacturing processes are limited by the maximum exposure area of an exposure machine, requiring multiple masks and exposure processes to form patterns outside the shot area, hindering the development of large die technology.
Innovation Solution
A semiconductor stitching structure and manufacturing method that minimizes the stitching region by positioning alignment marks within the component layout region, allowing for reduced stitching area and increased component density through overlapping mask patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple masks and exposure processes are used to form patterns outside the shot area, then the pattern formation capability is improved, but the stitching area increases
Solution Approach 1:
The invention extracts the alignment mark function from the stitching region by placing alignment marks within the component layout region. This separation allows the stitching region to be minimized to only what is necessary for pattern stitching, while alignment functions are performed elsewhere, thereby reducing the overall stitching area required.
Solution Approach 2:
The invention changes the spatial arrangement by placing alignment marks in the component layout region rather than in the stitching region. This dimensional repositioning allows the stitching regions of adjacent masks to overlap more efficiently, reducing the total stitching area while maintaining alignment capability.
2Quantity of substance
If the die area is increased to accommodate more components, then the component density is improved, but the exposure area limitation is worsened
Solution Approach 1:
The invention segments the large die pattern into multiple smaller patterns that can be formed by separate masks within the exposure machine's shot area. By using multiple masks with minimized stitching regions, the system can create large-area dies that exceed the single-exposure capability, effectively segmenting the overall pattern formation into manageable portions.
Solution Approach 2:
The invention merges multiple exposure processes and mask patterns to achieve a final large-area die pattern. By combining several smaller exposed areas with minimized stitching regions, the system creates a unified large die that accommodates higher component density while working within exposure area limitations.
3Area of stationary object
If the stitching region area is reduced, then the component layout area is improved, but the alignment precision is worsened
Solution Approach 1:
The invention extracts the alignment function from the stitching region and places alignment marks within the component layout region. This allows the stitching region to be minimized without compromising alignment precision, as alignment is performed separately using the extracted alignment marks positioned in the component layout area.
Data Source
AI summary
The invention provides a semiconductor stitching structure, which comprises a substrate, a first mask pattern is defined on the substrate, the first mask pattern comprises a first component layout region and a first stitching region, and a second mask pattern is defined on the substrate, the second mask pattern comprises a second component layout region and a second stitching region, and an overlapping stitching region, wherein the overlapping stitching region is the overlapping part of the first stitching region of the first mask pattern and the second stitching region of the second mask pattern, and a plurality of bridging wires located on the substrate in the overlapping stitching region, and a plurality of alignment marks located in the first component layout region on the substrate.