Semiconductor Stitching Accuracy via Overlay Inspection Marks
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Solution Overview
Problem
Current stitching exposure methods for large semiconductor devices face challenges in achieving high stitching accuracy, leading to potential circuit disconnections and increased device size due to fixed stitch positions, which restricts element layout and can result in visually disturbing image artifacts.
Innovation Solution
The method involves using first and second inspection mark regions with overlapping element regions of different areas, allowing flexible positioning of stitches by aligning overlay inspection marks on separate masks to form patterns with varying areas, thereby improving stitching accuracy and reducing the visibility of stitches in critical image regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single mask is used to form overlay inspection marks and alignment marks, then stitching accuracy is improved, but the position of the stitch becomes fixed and cannot be flexibly set
Solution Approach 1:
The patent divides the inspection mark formation into multiple masks: a first mask for forming overlay inspection marks and a second mask for forming alignment marks. This segmentation allows the inspection mark region to be separated from the element region, enabling flexible stitch position selection while maintaining high stitching accuracy through the overlay inspection marks.
2Area of stationary object
If stitching exposure is used to form large semiconductor devices, then the device area is increased, but stitching accuracy decreases leading to circuit disconnections
Solution Approach 1:
The patent performs preliminary formation of overlay inspection marks using a first mask before forming the element patterns. These pre-formed inspection marks serve as reference points for subsequent alignment, enabling high-precision stitching when combining multiple exposed regions to create large semiconductor devices.
Solution Approach 2:
The overlay inspection marks act as intermediary reference elements between different exposed regions. By providing these intermediate reference points, the patent enables accurate alignment and stitching of multiple regions without direct dependency on mask positioning accuracy alone.
3Manufacturing precision
If the stitch position is fixed, then stitching accuracy is maintained, but element layout is restricted and device size increases
Solution Approach 1:
The patent segments the mask system into multiple specialized masks: a first mask for overlay inspection marks, a second mask for alignment marks, and additional masks for element patterns. This segmentation decouples the inspection function from the element formation, allowing flexible element layout and stitch position selection while maintaining stitching accuracy.
4Productivity
If elements are arranged at narrow intervals, then device integration is increased, but misalignment at the stitch becomes apparent causing visual artifacts
Solution Approach 1:
The patent incorporates overlay inspection marks that provide feedback on alignment accuracy. By using these marks to measure and compensate for misalignment, the system can achieve high-precision stitching even when elements are arranged at narrow intervals, preventing visible artifacts in the final device.
Data Source
AI summary
A semiconductor device includes first and second inspection mark regions having the same pattern including a plurality of overlay inspection marks, a first element region having a portion overlapping with the first inspection mark region, and a second element region having a portion overlapping with the second inspection mark region. The first and second element regions are adjacent to each other and have different areas. The first element region includes a first pattern aligned with a plurality of first overlay inspection marks. The second element region includes a second pattern aligned with a plurality of second overlay inspection marks.