Semiconductor Storage Allocation Based on IP Core Access Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with multiple IP cores and storage devices, access stagnation occurs due to concentration of access on a single storage device, leading to bandwidth exceeding maximum per channel and resulting in dropped frames or interrupted audio during high-quality image or sound processing.
Innovation Solution
A semiconductor device determines if access timings between IP cores are the same and allocates different storage devices to each IP core to prevent access concentration, using a configuration information acquiring unit and an allocation determining unit to manage storage device allocation based on access timing information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple IP cores access a single storage device, then the system can be simplified with fewer storage devices, but access stagnation occurs due to concentration of access to one storage device
Solution Approach 1:
The patent segments the storage resources by allocating different storage devices to different IP cores based on their access timing characteristics. IP cores with similar access timings are assigned to different storage devices, dividing the storage access load across multiple devices rather than concentrating it on a single device.
Solution Approach 2:
The patent changes the allocation parameter from random or uniform distribution to timing-based allocation. By analyzing access timing parameters of IP cores and allocating storage devices accordingly, the system optimizes access patterns and prevents concentration of access on single storage devices.
2Productivity
If access allocation is optimized to prevent stagnation, then access efficiency improves, but the allocation process becomes more complex requiring timing analysis
Solution Approach 1:
The patent performs preliminary analysis of access timings during the allocation phase before actual operation begins. By determining and storing the access timing characteristics of each IP core in advance, the system can make optimal allocation decisions without requiring complex real-time analysis during operation.
Solution Approach 2:
The allocation mechanism automatically analyzes access timings and performs optimization without requiring external intervention. The system self-determines the optimal storage device allocation based on the access timing parameters of IP cores, making the complex allocation process transparent and automated.
3Productivity
If storage devices are allocated to prevent access concentration, then access stagnation is suppressed, but more storage devices are required
Solution Approach 1:
The patent implements dynamic allocation where storage devices are assigned to IP cores based on their access timing characteristics. This dynamic approach allows the system to efficiently utilize existing storage devices by matching them to appropriate IP cores, rather than requiring a fixed one-to-one mapping that would increase the number of storage devices needed.
Data Source
AI summary
A semiconductor device includes a plurality of IP cores, a plurality of storage devices, a configuration information acquiring unit that acquires configuration information for specifying a timing when the IP core accesses the storage device, and an allocation determining unit that determines the storage device allocated to the IP core. The configuration information acquiring unit acquires configuration information regarding a first IP core and configuration information regarding a second IP core. The allocation determining unit determines, based on the configuration information, whether an access timing by the first IP core is the same as an access timing by the second IP core, and when it is determined that the access timings are the same, determines allocation in such a way that the storage device allocated to the first IP core becomes different from the storage device allocated to the second IP core.


