Semiconductor Storage Device Bit Line Grouping for Read Speed
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Solution Overview
Problem
Current semiconductor storage devices face challenges in achieving high-speed operations and reducing bit error rates during read operations, particularly in managing threshold voltage distributions across memory cell transistors.
Innovation Solution
The semiconductor storage device employs a configuration with a memory cell array and control circuit that groups bit lines into bit line groups, allowing for selective read operations by setting threshold voltages of group-selection transistors, which enables efficient data retrieval and reduces bit error rates through precise voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read operations are performed on all bit lines to ensure data retrieval, then data completeness is improved, but operation speed deteriorates due to unnecessary data transfer
Solution Approach 1:
The patent divides bit lines into multiple bit line groups (first bit line group, second bit line group, etc.) and performs read operations selectively on only the required groups. This segmentation allows the system to read only necessary data portions rather than all bit lines, improving operation speed while maintaining data completeness for the required information.
Solution Approach 2:
The patent applies different read operation strategies to different bit line groups based on their specific requirements. By setting threshold voltages of group-selection transistors differently for each bit line group, the system optimizes read operations locally for each group, transferring only necessary data and avoiding unnecessary transfers from other groups.
2Manufacturing precision
If threshold voltage distribution is widened to improve manufacturing tolerance, then manufacturing precision is improved, but bit error rate worsens
Solution Approach 1:
The patent applies different threshold voltage settings to group-selection transistors in different bit line groups. By locally optimizing threshold voltages for each group based on specific read requirements, the system maintains precise voltage control while accommodating manufacturing variations, thereby reducing bit errors in the actually read data.
Solution Approach 2:
The patent changes threshold voltage parameters of group-selection transistors dynamically based on which bit line groups need to be read. By adjusting these voltage parameters according to operational requirements, the system optimizes the balance between manufacturing tolerance and bit error reduction.
3Reliability
If all memory strings are accessed during read operations to ensure data retrieval, then data completeness is improved, but energy consumption worsens
Solution Approach 1:
The patent segments the memory access space into different bit line groups and selectively activates only the groups containing required data. This segmentation prevents energy-consuming access operations on memory strings associated with unnecessary bit line groups, reducing overall energy consumption while ensuring complete retrieval of required data.
Solution Approach 2:
The patent performs read operations on only the necessary portion of bit line groups rather than all bit lines. By applying partial action (reading only required groups), the system retrieves sufficient data with reduced energy consumption compared to accessing all memory strings.
Data Source
AI summary
A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.