Semiconductor Storage Device Bit Line Grouping for Faster Read Operations
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Solution Overview
Problem
Current semiconductor storage devices, such as NAND flash memory, face limitations in processing speed due to inefficiencies in data transmission and read operations, particularly in cell reading and cache reading modes.
Innovation Solution
The semiconductor storage device incorporates a memory cell array with bit lines and sense amplifiers arranged in specific configurations, allowing for improved data transmission through a common bus connection, enabling faster data output and reducing the time required for read operations by implementing two distinct read modes: first cell reading and second cell reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted through a single common bus in conventional semiconductor storage devices, then device complexity is reduced, but processing speed and productivity deteriorate due to data transmission bottlenecks
Solution Approach 1:
The patent divides the single common bus into multiple separate bit line groups, each connected to its own sense amplifier. This segmentation allows parallel data transmission paths, eliminating the bottleneck of a single bus while maintaining manageable device complexity through modular organization of bit line groups and their corresponding sense amplifiers.
2Loss of time
If read operations are performed in conventional sequential manner, then device complexity remains low, but loss of time increases due to inability to initiate cache reading earlier
Solution Approach 1:
The patent introduces two dynamic read modes (first read mode and second read mode) that can be selectively activated based on operational requirements. The first read mode allows cache reading to be initiated earlier during cell reading operations, while the second read mode provides alternative timing characteristics. This dynamic switching capability reduces overall read operation time without permanently increasing device complexity.
Solution Approach 2:
In the first read mode, the system performs preliminary actions by initiating cache reading operations during the cell reading process itself, rather than waiting for cell reading to complete. This overlapping execution of operations reduces the total time required for data retrieval while maintaining control through the selective activation of read modes.
Data Source
AI summary
A semiconductor storage device includes a plurality of memory cells, bit lines respectively connected to the third memory cells, sense circuits respectively connected to the bit lines, latch circuits respectively connected to the sense circuits, and an input and output circuit connected to a first set of latch circuits via a first data line, a second set of latch circuit via a second data line, and a third set of latch circuits via a third data line. The bit lines are disposed in sequence in a first direction and a group of the sense circuits is disposed in sequence in a second direction crossing the first direction, and two bit lines that are not adjacent in the first direction are connected respectively to two sense circuits in the group that are adjacent in the second direction.