Semiconductor Storage Device Volatile Nonvolatile Memory Block Allocation
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Solution Overview
Problem
Nonvolatile semiconductor memory devices face inefficiencies in data management due to mismatched units for reading, writing, and erasing, leading to increased storage needs and reduced writing efficiency, particularly when managing small data updates in large-capacity systems.
Innovation Solution
A semiconductor storage device with a volatile memory area for sector-unit data and nonvolatile memory areas for page-unit and block-unit data, using a controller to manage data transfer and storage based on logical address alignment, optimizing data management by distinguishing between small and large units for efficient writing and erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is managed in small units (page size) to improve writing efficiency, then the correspondence list size increases, but the main memory cannot hold the entire address translation table, reducing address translation speed
Solution Approach 1:
The patent divides the address translation table into multiple segments stored in different memory areas. The main memory holds only frequently accessed translation entries, while less frequently accessed entries are stored in nonvolatile memory. This segmentation allows the system to maintain high address translation speed for common operations while accommodating large-capacity storage requirements.
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the host apparatus and the nonvolatile semiconductor memory. This buffer memory temporarily stores data and translation information, facilitating efficient address translation by holding intermediate results and reducing the need for frequent accesses to the full translation table in main memory.
2Device complexity
If the unit of data management is increased to block size to reduce correspondence list size, then address translation can be performed faster, but writing efficiency decreases due to larger erasure units
Solution Approach 1:
The patent implements dynamic data management where the system adaptively chooses between page-unit and block-unit management based on access patterns and data characteristics. Frequently accessed data is managed at the page level for efficient updates, while less frequently accessed data is managed at the block level to minimize erasure operations. This dynamic approach allows the system to optimize both address translation speed and writing efficiency according to actual usage patterns.
3Reliability
If wear leveling is performed to uniformly distribute data updating positions, then memory cell lifespan is extended, but the correspondence list becomes larger requiring more main memory
Solution Approach 1:
The patent applies different management strategies to different regions of the nonvolatile semiconductor memory based on local access patterns and wear characteristics. High-frequency access regions use page-unit management with optimized translation entries, while low-frequency access regions use block-unit management. This localized quality approach allows wear leveling to be applied effectively without requiring a uniformly large correspondence list across the entire memory space.
Data Source
AI summary
A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.