Semiconductor Storage Device Body Region Segmentation

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Solution Overview

Problem

Existing semiconductor storage devices with floating gate avalanche injection metal oxide semiconductor (FAMOS) technology face issues with off-leakage current in selection transistors leading to writing disturbance in non-selected cells due to floating potential at the body region.

Innovation Solution

A semiconductor storage device with a laminated substrate and memory cells comprising floating gate and selection transistors, where the first and second body regions are insulated from each other, allowing separate potential setting via body contact regions, enabling low-voltage writing operations without disturbing non-selected cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the potential at the body region of the selection transistor is floating potential, then the writing operation can be performed using FAMOS technology, but the off-leakage current in the selection transistor causes writing disturbance in non-selected cells

Engineering Contradiction:
Improvewriting operation capabilityVSAvoidwriting disturbance suppression
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The body region is segmented into two separate body regions: a first body region for the floating gate transistor and a second body region for the selection transistor. These two body regions are electrically isolated from each other, allowing independent potential control. This segmentation enables the floating gate transistor to operate with floating potential for FAMOS writing while the selection transistor's body region can be independently controlled to prevent off-leakage current and writing disturbance in non-selected cells

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An insulating film is introduced between the first body region and the second body region to act as an electrical barrier. This insulating film prevents charge carriers from moving between the two body regions, thereby blocking the off-leakage current path from the selection transistor to the floating gate transistor. This intermediary structure enables independent potential control of each body region, resolving the contradiction between FAMOS writing capability and writing disturbance suppression

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11563019B2Semiconductor storage device and electronic apparatus
Publication Date: 2023.01.24 SEIKO EPSON CORP
  • US11563019B2 patent drawing
  • US11563019B2 patent drawing
  • US11563019B2 patent drawing

AI summary

In a semiconductor storage device including a plurality of memory cells formed at a laminated substrate including a support layer, an insulating layer on the support layer, and a semiconductor layer on the insulating layer, the plurality of memory cells each include a floating gate transistor and a selection transistor. The floating gate transistor includes a first source region, a first drain region, a first body region, a first body contact region, a floating gate insulating film, and a floating gate electrode, and the selection transistor includes a second source region, a second drain region, a second body region, a second body contact region insulated from the first body contact region, a selection gate insulating film, and a selection gate electrode.