Semiconductor Storage Device Using Dielectric Breakdown for One-Time Programmability
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in achieving high data retention and memory density while preventing rewriting, particularly in NAND type flash memories which suffer from data retention issues due to charge storage time changes and the ability to rewrite data.
Innovation Solution
A semiconductor storage device that uses a memory cell transistor with a gate electrode and channel region, where a breakdown voltage is applied to cause dielectric breakdown between the gate electrode and channel region, allowing for high data retention and density while preventing rewriting by limiting the number of write operations per memory string.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND type flash memory uses floating gate or charge trap storage elements to achieve low manufacturing cost and high memory density, then memory density and manufacturing cost are improved, but data retention property deteriorates due to time change of charge stored in the storage element
Solution Approach 1:
The patent changes the storage mechanism from charge-based (floating gate/charge trap) to dielectric breakdown-based. By applying a breakdown voltage to cause dielectric breakdown between the gate electrode and channel region, the invention transforms the physical state of the insulating film from intact to broken down, creating a permanent conductive path that stores data without charge leakage issues.
Solution Approach 2:
The patent converts the typically harmful dielectric breakdown phenomenon into a useful data storage mechanism. Instead of avoiding breakdown as a failure mode, the invention deliberately induces controlled dielectric breakdown to create a permanent, irreversible state change that represents stored data, thereby eliminating data retention problems associated with charge storage.
2Adaptability or versatility
If NAND type flash memory allows rewriting operations to maintain flexibility, then adaptability is improved, but the ability to prevent rewriting deteriorates, making it unsuitable for OTPROM applications
Solution Approach 1:
The patent inverts the typical memory operation by making writing irreversible through dielectric breakdown. Instead of allowing repeated write-erase cycles, the breakdown of the insulating film creates a permanent state change that prevents further writing, thereby achieving OTPROM functionality while maintaining the physical structure advantages of NAND flash.
3Reliability
If mask ROM or eFuse is used to achieve one-time programmable functionality and data retention, then data retention property is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent makes the NAND flash memory cell serve multiple functions: it maintains the high-density three-dimensional structure of NAND flash while incorporating dielectric breakdown capability for OTPROM functionality. This universal approach eliminates the need for separate OTPROM structures like mask ROM or eFuse, reducing manufacturing complexity and cost while achieving both high density and one-time programmability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances data retention and memory density while preventing rewriting, addressing the limitations of NAND type flash memories by using dielectric breakdown to store data irreversibly, thus avoiding data retention problems and maintaining manufacturing cost efficiency.
Implementation Method 1
a breakdown voltage is applied to cause dielectric breakdown between the gate electrode and channel region
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes: a memory cell array including a memory cell transistor that is an electrically rewritable non-volatile semiconductor storage element. The memory cell transistor includes a gate electrode and a channel region adjacent the gate electrode. The semiconductor storage device includes a circuit configured to write the memory cell transistor by applying a breakdown voltage to cause dielectric breakdown between the gate electrode and the channel region.