Semiconductor Storage Device Common Bit Line Reference Current Circuit
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Solution Overview
Problem
Semiconductor storage devices with single-ended bit lines face challenges in miniaturization due to the need for a dummy digit line, leading to increased circuit size.
Innovation Solution
A semiconductor storage device design that includes a reference current supply unit for common bit lines not connected to data read target memory cells and a test control circuit that activates write and read word lines in a predetermined sequence, eliminating the need for a dummy bit line and reducing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy bit line is provided to enable data reading with single-ended bit lines, then data reading capability is achieved, but circuit size increases
Solution Approach 1:
The invention extracts and eliminates the dummy bit line from the circuit structure. By using the existing common bit line that is not connected to the data read target memory cell as the reference potential supply line instead of requiring a separate dummy bit line, the circuit size is reduced while maintaining the data reading capability through single-ended bit lines.
Solution Approach 2:
The common bit line is given multiple functions: it serves both as a signal transmission line for non-target memory cells and as a reference potential supply line for the sense amplifier. This multi-functionality eliminates the need for a dedicated dummy bit line, thereby reducing circuit size while preserving read functionality.
2Area of stationary object
If circuit size is reduced by eliminating dummy bit line, then miniaturization is achieved, but reference potential supply may be affected
Solution Approach 1:
The invention changes the operational parameters of the common bit line by controlling the word line activation timing. By activating the word line connected to the common bit line at a different timing (after a predetermined period) compared to the write operation timing, the common bit line maintains stable reference potential despite carrying signal currents during normal operation.
Solution Approach 2:
The sense amplifier is activated in advance to establish the reference potential on the common bit line before the actual data read operation begins. This preliminary action ensures that the reference potential is stable and ready for accurate differential measurement, compensating for the absence of a dedicated dummy bit line.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for miniaturization of semiconductor storage devices while maintaining read margin and accuracy, suppressing the increase in circuit size and enabling effective data reading without a dummy bit line.
Implementation Method 1
a sense amplifier that amplifies a potential difference between the first and second common bit lines
Implementation Method 2
a reference current supply unit that supplies a reference current to a common bit line from among first and second common bit lines
Data Source
AI summary
Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.