Semiconductor Storage Device Cutout for Chip Stacking Reliability
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Solution Overview
Problem
Current semiconductor storage devices face challenges in achieving high integration of memory chips while maintaining reliability, as the stacking of chips with overlapping pads and wires can lead to contact issues and decreased reliability due to the complexity of wire placement and chip alignment.
Innovation Solution
The semiconductor storage device incorporates a cutout portion on the semiconductor chips to avoid contact between wires and chips, allowing for increased integration without displacing the chips, using adhesion layers to maintain alignment and connection, and employing a resin to protect the components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are stacked with overlapping pads and wires to achieve high integration, then integration density is improved, but reliability deteriorates due to contact issues and alignment complexity
Solution Approach 1:
The patent extracts the problematic overlapping region by providing a cutout portion in the upper chip that removes the pad and wire from the area where they would contact the lower chip. This extraction eliminates the source of contact issues while preserving the stacking configuration for high integration.
Solution Approach 2:
The patent segments the chip structure by introducing a cutout portion that divides the chip into regions with different functions - the main body retains pads and wires for electrical connection, while the cutout region is removed to prevent contact with the lower chip. This segmentation allows simultaneous achievement of high integration and reliability.
2Manufacturing precision
If chips are stacked with precise alignment to maintain wire-chip contact, then electrical connection is improved, but manufacturing complexity increases due to alignment requirements
Solution Approach 1:
The cutout portion extracts the problematic alignment-critical region, allowing chips to be stacked without requiring precise alignment of pads and wires between layers. The remaining structures can be aligned with standard tolerances while the cutout ensures no contact occurs regardless of minor misalignments.
3Reliability
If cutout portion is provided to avoid contact between wires and chips, then reliability is improved, but chip area is reduced
Solution Approach 1:
The patent addresses the area loss by utilizing the vertical dimension - the cutout portion is configured in the thickness direction to prevent contact, allowing the horizontal area to be minimized rather than maximized. This dimensional approach allows compact chip design while maintaining reliability.
Solution Approach 2:
The cutout portion is strategically positioned only in the specific region where wire-chip contact would occur, rather than removing entire pads or wires. This localized modification maintains the necessary electrical connection area while preventing contact only where harmful.
Data Source
AI summary
A semiconductor storage device according to an embodiment includes a substrate, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a first surface contacting with the substrate, a second surface on an opposite side to the first surface, and a first pad provided on the second surface. The second semiconductor chip includes a third surface contacting with the second surface, a fourth surface on an opposite side to the third surface, and a cutout portion. The cutout portion is provided at a corner portion where the third surface crosses a lateral surface between the third surface and the fourth surface. The cutout portion overlaps with at least a part of the first pad as viewed from above the fourth surface.