Semiconductor Storage Device Data Latch System for High-Speed Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies in data transfer rates due to limitations in simultaneously performing read and write operations, as they typically require sequential execution and cannot recognize individual data latches for optimized operations.
Innovation Solution
A semiconductor storage device with a data latch system that includes multiple data latch units capable of holding addresses and data, allowing for efficient data transfer by varying the number of banks based on data transfer rates and using ReRAM memory cells to enhance read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential read and write operations are used in existing memory systems, then device complexity is reduced, but data transfer rate and productivity deteriorate
Solution Approach 1:
The memory system is divided into multiple banks (first bank and second bank), each with independent data latches. This segmentation allows parallel read and write operations to occur simultaneously in different banks, thereby increasing data transfer rate without requiring a single complex centralized control structure.
Solution Approach 2:
Data latches are introduced as intermediary components between the memory cells and the external interface. These latches temporarily hold data during transfer operations, enabling the memory system to perform read and write operations simultaneously by buffering data in the latches, thus improving productivity while maintaining manageable device complexity.
2Productivity
If multiple data latch units are used to enable simultaneous operations, then data transfer efficiency is improved, but device complexity increases
Solution Approach 1:
Each data latch unit is designed to perform multiple functions: holding read data, holding write data, and associated address latching. This multi-functionality reduces the need for separate dedicated latches for each operation type, thereby improving data transfer efficiency while controlling the overall number of latch units required in the system.
Solution Approach 2:
Data latches prepare and hold data in advance before actual memory operations are executed. By pre-latching addresses and data in the bank-specific latches before read/write operations, the system enables simultaneous operations without requiring complex real-time coordination, thus improving efficiency while keeping the latch structure manageable.
3Speed
If ReRAM memory cells are used to enhance read and write operations, then speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The memory array is divided into multiple banks with ReRAM cells, allowing parallel access to different segments. This segmentation enables high-speed operations by distributing the load across multiple independent ReRAM banks, achieving speed improvements while reducing the precision burden on any single ReRAM cell fabrication process.
Solution Approach 2:
The system utilizes the resistive state changes in ReRAM cells (high resistance and low resistance states) to represent binary data. By leveraging this parameter change mechanism and combining it with bank-based parallel architecture, the system achieves high read/write speeds while the manufacturing precision requirements are managed through the redundancy and parallelism provided by multiple banks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-speed data transfer by allowing simultaneous read and write operations and optimizing data handling through the use of multiple data latch units and ReRAM memory cells, improving data transfer efficiency compared to traditional systems.
Implementation Method 1
memory cells (Resistance Random Access Memory: ReRAM) each including a rectifying device (diode) and a variable resistance element
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a memory cell array, a data latch group. The memory cell array comprises a plurality of memory cells. The data latch group holds a first address or a second address of the memory cell and data. The data latch group comprises a first data latch unit and a second data latch unit, the first data latch unit holds write data to be written to any of the memory cells or read data read from the memory cell array and the first address or the second address, while the second data latch unit holds second write data or read data.