Semiconductor Storage Device Defect Detection via Autonomous Evaluation
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in detecting potential defects during evaluation, which can lead to early failures after shipment, as conventional evaluation methods may miss defects that become apparent later due to factors like program disturb, read disturb, and data retention deterioration.
Innovation Solution
The semiconductor storage device incorporates a memory controller that operates in two modes: a normal mode for standard operation and an autorun mode during evaluation, where it autonomously performs data erase, write, and read operations to identify defective blocks by using error correction codes and shifting read levels to correct errors, thereby detecting and isolating defective blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional evaluation methods are used, then manufacturing process is simple, but potential defects are not detected leading to early failures after shipment
Solution Approach 1:
The patent applies preliminary action by performing comprehensive data erase, write, and read operations on memory blocks before shipment. The memory controller autonomously executes evaluation sequences that stress-test each block, detecting potential defects early. This pre-evaluation identifies blocks that might fail under actual operating conditions, preventing early failures after the device reaches the customer.
Solution Approach 2:
The memory controller performs self-diagnosis and self-evaluation by autonomously executing erase, write, and read operations on the memory blocks without external intervention. The controller reads back the written data, compares it with the original data, and identifies defective blocks through error detection codes. This self-service evaluation mechanism enables comprehensive defect detection while maintaining manufacturing simplicity.
2Measurement precision
If comprehensive evaluation operations are performed on all blocks, then defect detection accuracy improves, but evaluation time increases
Solution Approach 1:
The patent segments the memory device into multiple independent blocks and evaluates them separately. The memory controller divides the comprehensive evaluation task across all blocks, performing erase, write, and read operations on each block individually. This segmentation allows parallel processing of multiple blocks, maintaining high defect detection accuracy while reducing total evaluation time compared to sequential evaluation of the entire memory space.
3Measurement precision
If error correction codes are used to correct read errors, then data read accuracy improves, but device complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where the memory controller reads data from memory blocks, compares the read data with the originally written data, and uses error detection codes to identify discrepancies. When errors are detected, the controller requests re-reading of the affected blocks and applies error correction by comparing multiple reads. This feedback loop ensures high data read accuracy while keeping the correction logic integrated within the existing controller architecture, minimizing additional complexity.
Data Source
AI summary
According to one embodiment, a semiconductor memory stores a program for causing a memory controller to operate in at least one of first and second modes. In the first mode, for each of the blocks, the memory controller autonomously erases and writes data and reads the written data, and determines that the block or the semiconductor storage device is defective when a count of errors in the read data exceeds a correction capability or a threshold. In the second mode, when error correction of read substantial data fails, the memory controller reads the substantial data which failed in the error correction using a read level shifted from the present read level.