Semiconductor Storage Device Differential Sense Amplifier Offset Compensation
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Solution Overview
Problem
In MRAM and ReRAM semiconductor storage devices, the varying wiring resistances across memory cells lead to incorrect logic level detection when reading data with a single reference voltage, necessitating adjustments in reference voltage and the use of self-reference methods to mitigate this issue.
Innovation Solution
A semiconductor storage device with a differential circuit that adjusts output signals based on voltage differences between nodes, utilizing offset currents to shift voltages and enable accurate data detection by using previous read data as a reference signal, thereby compensating for resistance variations across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reference voltage is used for reading data from all memory cells, then the device complexity is reduced, but the measurement precision of data logic levels becomes incorrect due to varying wiring resistances
Solution Approach 1:
The sense amplifier uses the previously read data signal as a reference signal for detecting the current data, allowing the system to self-adjust without external intervention. The output signal from the preamplifier is fed back to serve as the reference voltage for the next reading operation, enabling the circuit to automatically compensate for wiring resistance variations.
Solution Approach 2:
The patent implements feedback by using the output signal from the preamplifier (which contains information about the previously read data) as the reference signal for the sense amplifier. This feedback mechanism allows the system to continuously adjust the reference voltage based on actual reading conditions, compensating for variations in wiring resistance across different memory cell locations.
2Measurement precision
If self-reference method is used to adjust reference voltage, then the measurement precision of data logic levels is improved, but the read speed decreases due to additional reading operations
Solution Approach 1:
The preamplifier performs preliminary amplification and signal preparation before the data is read by the sense amplifier. By pre-processing the signal and using this pre-amplified output as the reference, the system eliminates the need for separate reference voltage generation operations, thereby maintaining fast read speeds while ensuring accurate data detection.
Solution Approach 2:
The patent merges the reference voltage generation function with the data reading function by using the preamplifier output to serve dual purposes: as an amplified signal for data detection and as a reference voltage for the sense amplifier. This consolidation eliminates the need for separate reference voltage reading operations, achieving both high speed and high precision.
3Measurement precision
If self-reference method is used to adjust reference voltage, then the measurement precision of data logic levels is improved, but the power consumption increases
Solution Approach 1:
The preamplifier output signal serves multiple functions simultaneously: it acts as the amplified data signal for detection and as the reference voltage for the sense amplifier. This multi-functionality eliminates the need for separate reference voltage generation circuits and operations, thereby reducing overall power consumption while maintaining accurate data detection.
Solution Approach 2:
The system uses its own output signal from the preamplifier to serve as the reference voltage, eliminating the need for external reference voltage generation. This self-service approach reduces the number of active components and operations required, thereby lowering power consumption while ensuring precise data logic level detection.
Data Source
AI summary
In a memory, a first node holds first data from a first cell. A second node holds second data from a second cell near the first cell. A differential circuit includes a first current path passing a first current corresponding to a voltage of the first node and a second current path passing a second current corresponding to a voltage of the second node, and outputs an output signal corresponding to a voltage difference between the first and the second nodes from an output part. A first register latches the output signal and output the signal as a hold signal. A first offset part is connected to the first current path and offsets the first current when the hold signal has a first logic level. A second offset part is connected to the second current path and offsets the second current when the hold signal has a second logic level.