Semiconductor Storage Device Layout for Reduced RC Time Constant
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Solution Overview
Problem
Current semiconductor storage devices, such as NAND flash memories, face challenges in improving processing performance due to increased wiring resistance and capacitance, leading to longer data transmission times and increased chip area, which can result in reduced efficiency in read and write operations.
Innovation Solution
The implementation of a 3-dimensional stacked NAND flash memory design where sense amplifier units and data registers are arranged on both sides of the BL hookup circuit, with each sense amplifier unit and data register connected to an exclusive data bus, reducing the length of the data bus and thereby decreasing the RC time constant, and optimizing the layout to minimize the distance between the BL hookup circuit and sense amplifier units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sense amplifier units and data registers are arranged on one side of the BL hookup circuit, then the layout is simpler, but the data bus length increases leading to longer RC time constant
Solution Approach 1:
The patent transitions from a one-sided linear arrangement to a two-sided symmetric arrangement around the BL hookup circuit. By placing sense amplifier units and data registers on both sides of the BL hookup circuit, the data bus length is effectively halved, reducing the RC time constant and improving data transmission speed without significantly increasing layout complexity
2Speed
If data bus length is reduced, then RC time constant decreases improving speed, but circuit layout becomes more constrained
Solution Approach 1:
The patent employs asymmetric placement within the symmetric framework - while sense amplifier units are positioned on both sides of the BL hookup circuit, the data registers are selectively placed only on one side. This asymmetric arrangement within the overall symmetric structure reduces data bus length for critical signals while maintaining reasonable layout flexibility for non-critical connections
3Area of stationary object
If chip area is increased, then more components can be accommodated, but wiring resistance and capacitance increase leading to longer transmission times
Solution Approach 1:
The patent segments the data bus into multiple shorter segments by placing data registers at strategic positions on both sides of the BL hookup circuit. This segmentation reduces the length of each individual bus segment, thereby reducing the cumulative RC time constant and improving signal transmission speed without requiring a proportional increase in total chip area
Data Source
AI summary
A semiconductor storage device includes a hookup circuit including first and second circuits connected respectively to first and second bit lines, a first circuit group including a first sense amplifier circuit connected to the first circuit and a first data register connected to the first sense amplifier circuit, a second circuit group including a second sense amplifier circuit connected to the second circuit and a second data register connected to the second sense amplifier circuit, and a memory cell array that is above the hookup circuit and the first and second circuit groups and includes a first memory cell connected to the first bit line and a second memory cell connected to the second bit line. The first circuit group, the hookup circuit, and the second circuit group are arranged in sequence along a first direction that is parallel to a surface of the semiconductor substrate.