Semiconductor Storage Device Erasing Operation Voltage Control
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in efficiently performing erasing operations, particularly in managing the voltage levels applied to conductive layers and word lines, which can lead to rapid deterioration of tunnel insulating films.
Innovation Solution
The semiconductor storage device employs a controlled erasing operation that involves increasing the first voltage supplied to the bit line and source line from a reference voltage to an erase voltage level, while simultaneously increasing the second voltage supplied to the word lines to the same erase voltage level. This is followed by maintaining the first voltage at the erase level and gradually decreasing the second voltage to a reference level, thereby reducing the threshold voltages of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage is applied to word lines during erasing operation, then erasing efficiency is improved, but tunnel insulating film deterioration accelerates
Solution Approach 1:
The patent applies preliminary action by raising the bit line voltage to the erase voltage level before applying the erase voltage to the word line. This sequence prepares the tunnel insulating film by establishing a high voltage environment on both sides of the film simultaneously, preventing sudden voltage differential shocks that would cause film deterioration, while still achieving effective erasure.
Solution Approach 2:
The patent implements beforehand cushioning by maintaining the bit line at erase voltage level during the word line voltage transition. This creates a voltage cushion or buffer that absorbs the stress of voltage changes, preventing excessive electric field formation across the tunnel insulating film that would lead to film breakdown, while preserving erasing effectiveness.
2Reliability
If voltage difference between channel and word lines is reduced, then tunnel insulating film deterioration is minimized, but erasing operation effectiveness may be compromised
Solution Approach 1:
The patent applies equipotentiality by raising the bit line voltage to the same erase voltage level as the word line voltage during erasing operation. This creates an equipotential condition across the tunnel insulating film, minimizing the voltage difference between the channel and word lines, thereby reducing electric field stress on the film while maintaining effective erasure through the controlled voltage application sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the voltage difference between the channel and the word lines, minimizing the number of holes passing through the tunnel insulating film and thereby slowing down its deterioration, while effectively reducing the threshold voltages of memory cells.
Implementation Method 1
minimizing the number of holes passing through the tunnel insulating film
Data Source
AI summary
According to one embodiment, in a semiconductor storage device, during an erasing operation, a voltage supplied to at least one of a first wiring and a second wiring is set as a first voltage, and a voltage supplied to a first conductive layer is set as a second voltage. The erasing operation includes a first operation period in which the first voltage is increased from a first reference voltage to a first erase voltage and the second voltage is increased from a second reference voltage to a second erase voltage. In a second operation period of the erasing operation, the first voltage is maintained at the first erase voltage and the second voltage is decreased from the second erase voltage to the second reference voltage (or a first level voltage larger than the second reference voltage) after the first operation period.