Semiconductor Storage Device Preventing Erroneous Writing
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Solution Overview
Problem
NAND flash memory devices face challenges in writing multiple threshold voltages efficiently without erroneous writing to non-selected cells, particularly when storing multilevel data, due to the need for high write voltages and the risk of non-selected cells being written to.
Innovation Solution
A semiconductor storage device with a memory cell array and a control circuit that applies a first potential to a well region, then sets it to a lower potential, and uses a predetermined voltage on word lines to perform a write operation, ensuring the channel region of non-selected cells remains high, preventing erroneous writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high write voltage is applied to a selected word line to write to a high threshold, then the write capability is improved, but non-selected cells connected to the same word line are erroneously written to
Solution Approach 1:
The patent applies different potentials to different regions: a high first potential is applied to the well region to boost the channel region, while a low second potential is maintained on non-selected word lines. This local differentiation allows the selected cells to receive sufficient write voltage through the boosted channel, while non-selected cells remain protected due to their low word line potential, resolving the contradiction between write capability and prevention of erroneous writing.
2Reliability
If the potential on non-selected word lines is set high to prevent erroneous writing, then writing accuracy is improved, but cells in the same NAND unit as selected cells are actually written to
Solution Approach 1:
The patent implements local quality by applying the high first potential specifically to the well region rather than uniformly to all word lines. This localized potential application boosts the channel region potential only where needed for selected cells, preventing erroneous writing to cells in the same NAND unit while maintaining writing accuracy for selected cells.
Solution Approach 2:
The patent segments the voltage application strategy: the well region receives a high first potential to boost the channel, while non-selected word lines maintain a low second potential. This segmentation allows differentiated control over selected versus non-selected cells within the same NAND unit, preventing erroneous writing while maintaining write capability.
3Reliability
If the channel region potential is set high to prevent erroneous writing, then writing accuracy is improved, but write speed decreases due to repeated program and verify operations
Solution Approach 1:
The patent performs preliminary action by applying the high first potential to the well region before the write operation begins. This pre-boosting of the channel region potential creates favorable conditions for writing, allowing the write operation to proceed more efficiently with fewer verify cycles, thereby improving write speed while maintaining writing accuracy.
Data Source
AI summary
A memory cell array has a number of memory cells which are connected to word lines and bit lines and are arranged in a matrix form, each of the memory cells storing one of n levels (n is a natural number of 2 or more). A control circuit controls the potentials on the word lines and the bit lines in accordance with input data to write data to the memory cells. The control circuit is adapted to, at the write time, first apply a first potential to a well region or substrate in which the memory cells are formed, then set the well region or substrate to a second potential lower than the first potential, and next apply a predetermined voltage to the word lines to thereby perform a write operation.