Semiconductor Storage Device with Dual-End Transistor Biasing
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Solution Overview
Problem
Resistance change memories, such as PCM and ReRAM, require large write currents, leading to significant voltage drops in word and bit lines, which prevents efficient heating of memory cells far from the power source, making it difficult to write data into these cells effectively.
Innovation Solution
The semiconductor storage device employs transistors alternately connected to the ends of word lines, allowing a selection voltage to be applied simultaneously to adjacent memory cells, enabling thermal energy transfer between cells to efficiently heat and write data, even for cells far from the transistors, thereby reducing energy consumption and voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a large write current is applied to heat memory cells for data writing, then the heating effect is sufficient, but the voltage drop in word lines and bit lines becomes large, preventing memory cells far from the power source from being efficiently heated
Solution Approach 1:
The patent divides the memory cell array into multiple banks, with each bank having its own dedicated power source. This segmentation allows each bank to operate independently with sufficient power, preventing the voltage drop problem that occurs when a single power source serves the entire array. Memory cells far from the central power source are no longer affected by cumulative voltage drops along long word lines and bit lines.
Solution Approach 2:
The patent introduces a third dimension by stacking multiple memory cell arrays vertically, with each layer served by its own power source. This three-dimensional architecture reduces the horizontal distance that power must travel through word lines and bit lines, thereby reducing voltage drops while still providing sufficient heating current to memory cells.
2Quantity of substance
If the memory array is extended to increase storage capacity, then more memory cells are available, but the voltage drop prevents memory cells far from the power source from being effectively written
Solution Approach 1:
By dividing the large memory array into multiple smaller banks, each with its own power source, the patent enables the system to accommodate a greater total number of memory cells while ensuring that no memory cell is too far from its dedicated power source. This segmentation maintains writing reliability across the entire extended array.
Solution Approach 2:
The vertical stacking of multiple memory cell layers, each with its own power source, allows the system to increase storage capacity by adding more memory cells in the vertical dimension rather than extending horizontal wiring. This approach maintains reliable data writing to all memory cells regardless of their horizontal distance from any single power source.
3Device complexity
If transistors are connected at one end of word lines only, then the circuit is simpler, but memory cells far from the transistor connection cannot be efficiently heated
Solution Approach 1:
The patent places power sources at multiple locations (both ends of word lines and at intermediate points) rather than relying on a single connection point. This segmentation of power delivery ensures that memory cells throughout the entire word line, regardless of distance from any single transistor, receive sufficient current for efficient heating.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable data writing into memory cells by utilizing thermal energy from adjacent cells, reducing current and voltage drop, and increasing the number of connectable memory cells per line, thus lowering bit cost.
Implementation Method 1
enabling thermal energy transfer between cells to efficiently heat and write data
Implementation Method 2
Since a resistance change memory heats memory cells to perform a write operation, a large write current is required
Data Source
AI summary
A memory includes first lines arrayed along a surface of a substrate. Second lines are arrayed along the surface of the substrate either above or below the first lines and intersecting with the first lines. Resistance change memory cells are provided to correspond to intersection regions between the first lines and the second lines, respectively. First switching elements are arranged on a side of first ends of the first lines and transmitting a first voltage for writing or reading data to at least one memory cell among the memory cells. Second switching elements are arranged on a side of second ends of the first lines on an opposite side to the first ends and transmitting the first voltage to at least another one memory cell among the memory cells. The first switching elements and the second switching elements are connected to different ones of the first lines, respectively.