Semiconductor Storage Apparatus Dynamic Resistance Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor storage apparatuses using anti-fuse elements face challenges in efficiently reading and writing data while maintaining electrostatic discharge (ESD) resistance, as the diffusion resistance used for protection reduces electric responsiveness and increases resistance values, affecting writing quality and productivity.
Innovation Solution
A semiconductor storage apparatus is designed with a first resistance connected in series to the power line for writing voltage and a second resistance connected in parallel via a drive element, allowing for reduced voltage drop during data access by connecting the resistances in parallel when a memory device is selected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diffusion resistance is connected in series to anti-fuse element for ESD protection, then ESD resistance is improved, but electric responsiveness deteriorates and voltage drop increases
Solution Approach 1:
The patent applies dynamics by making the resistance value changeable based on operational state. A transistor is introduced to dynamically switch between two resistance configurations: during normal operation the full series resistance provides ESD protection, while during read operations the transistor bypasses part of the resistance to reduce voltage drop and improve reading speed. This dynamic adaptation resolves the contradiction between ESD protection and reading efficiency.
Solution Approach 2:
The patent introduces a transistor as an intermediary element between the diffusion resistance and the anti-fuse element. This intermediary component acts as a controlled switch that can short-circuit the diffusion resistance when reading operations are performed, thereby eliminating the harmful voltage drop during reads while maintaining the ESD protection function during normal operation. The intermediary enables selective activation of protection versus performance modes.
2Reliability
If diffusion resistance is connected in series to anti-fuse element for ESD protection, then ESD resistance is improved, but writing energy efficiency deteriorates
Solution Approach 1:
The patent makes the resistance configuration dynamic by using a transistor to switch between high-resistance mode (for ESD protection) and low-resistance mode (for writing operations). During writing, the transistor activates to reduce the series resistance, thereby minimizing voltage drop and energy loss while maintaining sufficient ESD protection capability when the transistor is inactive.
Solution Approach 2:
The transistor serves as an intermediary that mediates between the conflicting requirements of ESD protection and writing efficiency. By controlling the transistor's conduction state, the system can eliminate the diffusion resistance's harmful effect during writing operations while preserving its protective function during idle or read states, thus reducing energy loss without compromising reliability.
3Manufacturing precision
If writing voltage is increased to improve writing quality, then writing quality is improved, but voltage drop across diffusion resistance increases
Solution Approach 1:
The patent applies dynamics by introducing a transistor that can switch the resistance configuration based on the operational phase. During writing operations, the transistor activates to bypass the diffusion resistance, allowing high writing voltage to be applied without excessive voltage drop. This dynamic switching enables maintaining high writing quality while minimizing energy loss during the actual writing process.
Data Source
AI summary
A semiconductor storage apparatus comprising a memory unit including one or more memory devices, the semiconductor storage apparatus further comprising a first resistance connected in series to a power line that supplies a writing voltage to the memory unit, a second resistance connected in parallel to the first resistance via a drive element, and a control unit configured to control the drive element to be driven into conduction to allow current to flow through the first resistance and the second resistance when a memory device of the one or more memory devices of the memory unit is selected.