Semiconductor Storage Circuit ECC Timing Equalization
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Solution Overview
Problem
Semiconductor storage circuits with ECC functions face challenges in maintaining high operating frequency and random accessibility due to the increased number of cycles required for write and read operations, as well as restrictions in input timing for commands, which are exacerbated in LSIs with embedded memory.
Innovation Solution
A semiconductor storage circuit with a memory core, ECC encoder, and ECC decoder, where the memory core is activated in response to each operation cycle, with ECC encoding and decoding performed in synchronization with a delayed clock signal to equalize delays and adjust timing for write and read operations, thereby reducing the number of cycles and preventing access collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC processing and memory access are performed in one operation cycle, then data reliability is improved, but operating frequency is restricted
Solution Approach 1:
The patent segments the operation cycle into distinct phases: a first operation cycle for command input and address registration, and a second operation cycle for memory core activation and data transfer. This segmentation allows ECC processing and memory access to be distributed across multiple cycles, preventing resource conflicts while maintaining data reliability.
Solution Approach 2:
The patent performs preliminary actions in the first operation cycle by registering the address in an address register before the memory core is activated. This preliminary address registration enables the memory core to be activated in the second operation cycle without delay, improving the overall speed while ensuring reliable ECC processing.
2Speed
If pipelining is used for memory access and ECC encoding/decoding, then operating frequency is improved, but random accessibility deteriorates
Solution Approach 1:
The patent implements a self-service mechanism where the address register automatically holds the address information after registration in the first operation cycle, and the memory core automatically activates in the second operation cycle using this held address. This self-service approach eliminates the need for complex control logic to manage random access requests, thereby maintaining ease of operation while improving operating frequency through pipelining.
3Reliability
If write command input is restricted to prevent access collisions, then data reliability is improved, but random accessibility deteriorates
Solution Approach 1:
The patent introduces dynamic timing control where the activation of the memory core is shifted to the second operation cycle, creating a dynamic separation between command input and memory access. This dynamic approach allows write commands to be freely input in the first operation cycle without causing access collisions, as the actual memory access occurs in the second cycle, thereby maintaining random accessibility while ensuring data reliability.
Data Source
AI summary
A semiconductor storage circuit includes a memory core which includes multiple memory cells; an error checking and correction (ECC) encoder; and an ECC decoder. The memory core is activated in response to input of a command for each operation cycle. The ECC encoder performs ECC encoding of input data which is input together with a write command and thus generates ECC data, and generates write data including the input data and the ECC data. The ECC decoder performs ECC decoding of read data which has been read from the memory core according to a read command, using ECC data included in the read data, and thus generates output data. An adjustment is made to equalize a delay from input of a write command until activation of the memory core and a delay from input of a read command until activation of the memory core.