Semiconductor Storage Electrode Formation via Dummy Region Copying
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Solution Overview
Problem
Conventional semiconductor manufacturing methods face challenges in maintaining process margins due to differences in critical dimensions between storage electrode regions at the middle and outermost zones of the cell region, leading to defects like bunker defects and column failures during the Self Aligned Contact process.
Innovation Solution
A method is introduced where a dummy region is formed around the cell region with patterns of the same size and shape as the cell region, using a sacrificial layer, etch stop pattern, and hard mask to ensure uniform process margins by preventing the formation of unnecessary storage electrode regions in the dummy area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the storage electrode region is formed at the outermost zone with a larger pattern CD to compensate for exposure weakness, then the pattern formation is improved, but the process margin is decreased due to CD difference between middle and outermost zones
Solution Approach 1:
The patent applies the copying principle by creating a dummy region that replicates the cell region's structure and dimensions. The dummy region includes dummy storage electrode contacts and dummy bit line contacts with the same critical dimensions as the real contacts, allowing the outermost patterns to be formed with consistent CD without requiring compensatory enlargement, thereby maintaining both manufacturing precision and process margin
Solution Approach 2:
The patent applies local quality by differentiating between the cell region and dummy region in terms of function while maintaining identical geometric properties. The dummy region is specifically designed with the same pattern dimensions as the cell region to provide uniform exposure conditions and process margins across all zones, eliminating the need for varying CD compensation
2Illumination intensity
If the pattern CD at the outermost zone is formed larger than the middle zone to ensure exposure, then pattern visibility is improved, but bunker defects and column failures occur due to inaccurate SAC process
Solution Approach 1:
The dummy region copies the cell region's pattern geometry exactly, including contact dimensions and spacing. This ensures that all regions, including outermost zones, receive uniform exposure intensity without requiring enlarged CD, thereby preventing bunker defects and column failures while maintaining adequate exposure
3Reliability
If dummy patterns are added around the cell region to secure process margin, then process margin is improved, but device complexity increases due to additional structures
Solution Approach 1:
The dummy region is created as a simplified copy of the cell region, using the same pattern library and fabrication processes. This approach secures process margin through uniform exposure conditions while minimizing device complexity by avoiding the need for specialized or additional process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach secures equal process margins between the cell and dummy regions, preventing defects and ensuring accurate formation of storage electrodes, thereby enhancing the quality of semiconductor devices.
Implementation Method 1
etching the exposed sacrificial oxide by using the hard mask pattern as a mask to form a storage electrode region at the cell region
Implementation Method 2
depositing a conductive layer in the storage electrode region to form a storage electrode contacting the first storage electrode contact of the cell region
Data Source
AI summary
A method for manufacturing semiconductor device includes forming an interlayer dielectric layer including a contact plug defined therein to electrically couple a semiconductor substrate on which a cell region and a dummy region are defined. A sacrificial layer is formed over the interlayer dielectric layer. An etch stop pattern is formed over the sacrificial layer, the etch stop pattern being vertically aligned to the dummy region. A storage electrode region through the sacrificial layer is defined to expose a first storage electrode contact of the cell region, the second storage electrode contact of the dummy region remaining covered by the sacrificial layer. A conductive layer is deposited within the storage electrode region to form a storage electrode contacting the first storage electrode contact of the cell region.