Semiconductor Storage Electrode Supporters for Capacitance and Stability

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Solution Overview

Problem

As semiconductor devices become highly integrated, the decreasing area of unit cells makes it challenging to secure sufficient capacitance, leading to potential bending or collapse of storage nodes.

Innovation Solution

The semiconductor device design includes a plurality of via structures, storage electrodes, and supporters with specific spacing and thickness configurations, along with a capacitor dielectric layer and plate electrodes, to enhance capacitance while preventing node bending or collapse. The supporters are arranged to connect different portions of the storage electrodes, ensuring the capacitor dielectric layer covers all necessary surfaces, and the storage electrodes have varying thicknesses to optimize capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the area of unit cell is decreased to achieve higher integration, then the integration density is improved, but the capacitance becomes insufficient

Engineering Contradiction:
Improveintegration densityVSAvoidcapacitance
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent transitions from a planar capacitor structure to a three-dimensional structure by introducing vertical storage nodes that extend through multiple layers. The storage nodes are formed as high-aspect-ratio structures penetrating through the capacitor dielectric layer, utilizing the vertical dimension to increase capacitance without expanding the horizontal unit cell area. This dimensional transition allows capacitance to be maintained or improved while achieving higher integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where the storage node is embedded within the via structure, and the capacitor dielectric layer surrounds the storage node. The supporters are positioned within the via structure to provide mechanical support. This nested arrangement maximizes the use of available space within the unit cell, allowing multiple functional elements to occupy the same horizontal footprint while maintaining sufficient capacitance.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If the storage node area is decreased to achieve higher integration, then the integration density is improved, but the storage node becomes prone to bending or collapse

Engineering Contradiction:
Improveintegration densityVSAvoidstructural stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces supporters as intermediary structures positioned within the via structure to provide mechanical support to the storage node. These supporters act as a mediator between the storage node and the via structure, preventing the high-aspect-ratio storage node from bending or collapsing while maintaining the reduced horizontal area needed for high integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The via structure is segmented into multiple portions with supporters positioned at different heights (first supporter at first height, second supporter at second height). This segmentation provides distributed mechanical support along the vertical extent of the storage node, enhancing structural stability throughout the entire height of the high-aspect-ratio storage node rather than relying on a single support point.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10121793B2Semiconductor device having supporters and method of manufacturing the same
Publication Date: 2018.11.06 SAMSUNG ELECTRONICS CO LTD
  • US10121793B2 patent drawing
  • US10121793B2 patent drawing
  • US10121793B2 patent drawing

AI summary

A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.