Semiconductor Storage Device Global Signal Line Grouping
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Solution Overview
Problem
The increasing number of bit lines or word lines in semiconductor storage devices leads to a larger arrangement area for decoders, and simply omitting transistors in multiplexers reduces controllability and flexibility in voltage application, potentially resulting in inappropriate voltage control for unselected lines.
Innovation Solution
The semiconductor storage device configures global signal lines to apply selection voltages to bit lines or word lines, with transistors connecting these lines to global signal lines and selection signal lines, allowing for reduced global word line count while maintaining control over unselected lines by applying non-selection voltages or floating them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bit lines or word lines is increased to enhance storage capacity, then the storage capacity is improved, but the arrangement area of the decoder increases
Solution Approach 1:
The patent divides the word lines into multiple groups, with each group managed by separate transistors that control connection to global word lines. This segmentation allows the decoder to handle more word lines without proportionally increasing the decoder area, as the grouping structure enables more efficient space utilization.
Solution Approach 2:
The patent introduces a hierarchical structure with global word lines and group-specific transistors, adding a dimensional layer to the traditional decoder architecture. This allows word lines to be organized in groups where transistors control connections from multiple word lines to shared global lines, reducing the overall decoder footprint while maintaining control over increased numbers of word lines.
2Area of stationary object
If transistors are omitted from the multiplexer to reduce arrangement area, then the decoder area is reduced, but the controllability and flexibility in voltage application deteriorates
Solution Approach 1:
The patent introduces global word lines as intermediary elements between the reduced decoder circuitry and the word lines. These global word lines act as mediators that carry selection signals to multiple word line groups, enabling the decoder to maintain voltage control flexibility with fewer transistors by using the global word lines as intermediate control carriers.
Solution Approach 2:
The global word lines serve multiple functions: they carry selection signals to multiple word line groups, enable voltage application to unselected lines for disturbance prevention, and provide a shared control pathway that reduces the need for dedicated transistors for each word line. This multi-functionality maintains control flexibility while reducing transistor count.
3Area of stationary object
If transistors are omitted to reduce decoder area, then the arrangement area is reduced, but the ability to control unselected bit lines or word lines deteriorates
Solution Approach 1:
By dividing word lines into groups with dedicated transistors for each group rather than individual transistors for each line, the patent maintains the ability to control unselected lines within each group while reducing total transistor count. The segmentation allows selective control at the group level, preserving reliability for preventing disturbances to unselected lines.
Solution Approach 2:
Global word lines serve as intermediaries that enable the reduced set of transistors to maintain control over unselected word lines. The global word lines carry control signals to multiple groups, ensuring that unselected lines receive appropriate voltages to prevent disturbances, thereby maintaining reliability despite fewer transistors.
Data Source
AI summary
A memory includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) lines, and second signal lines. A memory cell array includes memory cells. (m+2) or more global signal lines are configured to apply a selection voltage to any of the first signal lines. First transistors are provided to correspond to each of the first signal lines in one-to-one correspondence and are connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups, and are each connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. The first signal lines located at both ends of each of any two of the groups which are adjacent to each other are connected to mutually different ones of the global signal lines.