Semiconductor Storage Device Honeycomb Memory Cell Array Layout
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in reducing the size of memory cell arrays while maintaining equal distances between adjacent memory elements, which affects the overall device size and manufacturing efficiency.
Innovation Solution
The semiconductor storage device employs a configuration where memory elements, including magnetic tunnel junctions and select transistors, are arranged in a honeycomb pattern with specific distances between them, allowing for equal spacing and reduced cell size, utilizing a vertical transistor configuration and offsetting elements to minimize overlap and maximize contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory elements are arranged in a conventional rectangular grid pattern, then the layout is simple and easy to manufacture, but the area occupancy is larger and the device size increases
Solution Approach 1:
The patent transitions from a conventional two-dimensional rectangular grid arrangement to a three-dimensional stacked configuration where memory elements are arranged vertically across multiple layers. This dimensional change allows for equal spacing between adjacent elements while reducing the planar footprint, thereby decreasing area occupancy without compromising manufacturing simplicity
Solution Approach 2:
The patent implements a stacked memory structure where multiple layers of memory elements are nested vertically above each other. Each layer contains memory elements that are positioned to overlap or align with elements in adjacent layers, creating a nested configuration that maximizes space utilization and reduces overall device area while maintaining equal distances between elements
2Area of stationary object
If memory elements are placed closer together to reduce device size, then area occupancy decreases, but manufacturing precision requirements increase
Solution Approach 1:
By moving to a three-dimensional stacked arrangement, the patent reduces the planar distance between elements while distributing spacing requirements across multiple vertical layers. This allows for smaller overall device area while maintaining manageable spacing precision requirements through the vertical dimension
Solution Approach 2:
The patent employs asymmetric positioning where certain memory elements are deliberately offset from perfect alignment with elements in adjacent layers. This asymmetric arrangement optimizes spacing to achieve equal distances between all adjacent elements while facilitating manufacturing by avoiding overly stringent alignment requirements
3Area of stationary object
If memory elements are arranged in a honeycomb pattern with equal spacing, then area occupancy is reduced and device size decreases, but the layout complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements a honeycomb-like equal-spacing arrangement in three dimensions, where memory elements are positioned at vertices of tetrahedral or hexagonal patterns across multiple stacked layers. This vertical stacking of symmetric patterns achieves the equal-spacing honeycomb configuration while maintaining manufacturing ease through standardized layer replication
Solution Approach 2:
The patent creates a universal stacked memory structure where the same basic unit cell pattern is replicated across multiple layers with consistent spacing and positioning rules. This universal configuration allows for simplified manufacturing through standardization, reducing the complexity that would otherwise arise from implementing equal-spacing honeycomb patterns
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a denser memory cell array with reduced area occupancy, improved manufacturing precision, and enhanced contact areas between elements, leading to a more efficient and compact storage device.
Implementation Method 1
a second magnetic layer which is a ferromagnetic layer having a direction of easy magnetization that is perpendicular to a film surface and contains cobalt iron boron (CoFeB)
Implementation Method 2
a magnetic tunnel junction element MTJ...including a current path through which a current flows in a direction perpendicular to a film surface
Data Source
AI summary
A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.