Semiconductor Storage Device Horizontal Channel Layout

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Solution Overview

Problem

Conventional semiconductor storage devices with alternately stacked insulating films and word lines experience increased read time due to longer channel lengths and noise during read operations, especially in random read scenarios.

Innovation Solution

The semiconductor storage device configuration includes a channel portion parallel to the substrate surface, with a charge storage unit and gate wiring arrangement that shortens the channel length, ensuring stable data writing and reading by providing two channel current paths and optimizing the layout of pillars and insulating layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If insulating films and word lines are alternately stacked in the thickness direction to increase storage capacity, then the channel length increases, but the read time increases and read operation becomes slower

Engineering Contradiction:
Improvestorage capacityVSAvoidread time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent transitions from a vertical channel configuration (thickness direction) to a horizontal channel configuration (plane direction). The channel portion is formed to extend in the plane direction of the substrate rather than penetrating through the stacked body in the thickness direction, thereby shortening the effective channel length while maintaining the stacked memory structure for high capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the channel length increases due to stacked structure, then more memory layers can be accessed, but noise during read operations increases

Engineering Contradiction:
Improvememory layer accessibilityVSAvoidread operation noise
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

By reconfiguring the channel to extend in the plane direction rather than vertically, the patent reduces the channel length that generates noise during read operations, while the stacked body structure remains intact to provide access to multiple memory layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent separates the channel function from the vertical stacking direction. The channel portion is extracted and configured to extend horizontally in the plane direction, independent of the vertical word line stacking, thereby isolating the noise-generating channel from the vertical dimension where multiple layers are accessed.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If conventional vertical channel configuration is used, then stacked structure can be implemented, but random read operations become slower

Engineering Contradiction:
Improvestacked structure implementationVSAvoidrandom read speed
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent maintains the stacked body structure for ease of manufacture while changing the channel orientation to the plane direction. This dimensional change enables faster random read operations by shortening the channel length, achieving both manufacturing ease and improved performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11706921B2Semiconductor storage device
Publication Date: 2023.07.18 KIOXIA CORP
  • US11706921B2 patent drawing
  • US11706921B2 patent drawing
  • US11706921B2 patent drawing

AI summary

A semiconductor storage device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, a charge storage unit. The first wiring extends in a first direction along a surface of the substrate. The second wiring is aligned with the first wiring in a second direction intersecting with the first direction and extends in the first direction. The third wiring is in contact with the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting with the first direction and the second direction, and is aligned with the third wiring in at least the first direction. The charge storage unit is located between the third wiring and the fourth wiring.