Semiconductor Storage Device Isolation Layer Design
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Solution Overview
Problem
In three-dimensional non-volatile memory semiconductor storage devices, existing technologies face challenges in reliably isolating the uppermost conductive layers due to manufacturing differences, leading to incomplete isolation of select gate lines and increased device size, or electrical connectivity issues between select gate lines.
Innovation Solution
The semiconductor storage device employs an isolation layer that extends in the X direction within the stacked bodies and connects to the side surface of plate-shaped portions, ensuring reliable isolation of the uppermost conductive layers by connecting to the inner region between plate-shaped portions, thereby preventing electrical connectivity between select gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the isolation layer is extended to ensure reliable isolation of conductive layers, then isolation reliability is improved, but device size increases
Solution Approach 1:
The isolation layer is selectively extended only in regions where manufacturing variations require additional isolation coverage, rather than uniformly across the entire device. This localized extension approach ensures reliable isolation of conductive layers and prevents electrical connectivity between select gate lines only where needed, thereby improving isolation reliability without unnecessarily increasing overall device size.
2Volume of moving object
If the isolation layer is shortened to reduce device size, then device compactness is improved, but isolation reliability deteriorates
Solution Approach 1:
The isolation layer is designed with preliminary extended regions that anticipate potential manufacturing variations and positioning deviations. By pre-extending the isolation layer in critical areas before final assembly, the design ensures that even if manufacturing variations occur, the isolation reliability is maintained without requiring excessive extension across the entire device, thus achieving a balance between compactness and reliability.
3Ease of manufacture
If the isolation layer position varies due to manufacturing differences, then manufacturing flexibility is improved, but electrical connectivity between select gate lines increases
Solution Approach 1:
The isolation layer includes preliminary extended regions that proactively counteract the potential harmful effect of manufacturing variations. These extended regions are positioned to preemptively prevent electrical connectivity between select gate lines, even when the isolation layer position varies during manufacturing. This preliminary anti-action ensures that manufacturing flexibility is maintained while preventing the generation of harmful electrical connections.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes: first and second plate-shaped portions which extend in a stacking direction of each layer of a first stacked body and a first direction intersecting the stacking direction and are arranged between the first stacked body and a second stacked body on both sides of the second stacked body in a second direction intersecting the stacking direction and the first direction; and an isolation layer that penetrates at least the uppermost conductive layer among a plurality of conductive layers and isolates the uppermost conductive layer in the second direction. The isolation layer extends in a portion of the first stacked body in the first direction toward the second stacked body, and is connected to a side surface of the first plate-shaped portion from a first region on an inner side of the first and second plate-shaped portions.