Semiconductor Storage Device Latch Circuit Pipeline
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Solution Overview
Problem
Conventional semiconductor storage devices with separate core and interface chips face challenges in high-speed data transfer due to shared through-electrodes, leading to low efficiency and increased stray capacitance, which worsens with increased storage capacity.
Innovation Solution
Implementing a semiconductor storage device with separate core chips equipped with latch circuit units connected in a cascade to an interface chip, allowing for pipeline operation and separating through-electrodes to reduce stray capacitance and maintain constant electrode numbers across different chip layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If through-electrodes are shared by multiple core chips, then device complexity is reduced, but data transfer speed decreases and stray capacitance increases
Solution Approach 1:
The patent divides the through-electrode connections into separate dedicated pathways for each core chip. Instead of sharing common through-electrodes, each core chip has its own set of through-electrodes connected to the interface chip, eliminating signal interference and reducing stray capacitance effects on data transfer speed.
Solution Approach 2:
The patent introduces latch circuit units as intermediary components between core chips and the interface chip. These latch circuits buffer and manage data flow, allowing multiple core chips to operate independently through their own through-electrode connections while being coordinated by the interface chip, thus maintaining high speed without requiring complex direct interconnections.
2Ease of manufacture
If through-electrodes are shared by multiple core chips, then manufacturing process is simplified, but stray capacitance increases and prevents high-speed data transfer
Solution Approach 1:
The patent segments the electrical connection pathways by providing dedicated through-electrodes for each core chip. This physical separation reduces the parasitic capacitance between adjacent signal lines and eliminates crosstalk, thereby reducing stray capacitance effects while maintaining a relatively simple manufacturing process through standardized chip stacking.
Solution Approach 2:
The patent applies different connection configurations to different regions of the device. Each core chip region has its own dedicated through-electrode connections with optimized spacing and routing, allowing local optimization of stray capacitance reduction while maintaining overall manufacturing efficiency through modular assembly.
3Speed
If separate through-electrodes are provided for each core chip, then data transfer speed increases, but the position of through-electrodes changes for each chip making manufacturing impossible with the same mask
Solution Approach 1:
The patent designs each core chip with identical through-electrode patterns and configurations, making them universal and manufacturable using the same mask set. The latch circuit units and interface chip coordinate the operation of multiple identical core chips, allowing high-speed data transfer through standardized, repeatable manufacturing processes.
Solution Approach 2:
The patent uses identical copies of core chip designs with standardized through-electrode positions for all core chips in the device. This copying approach enables manufacturing with the same masks while maintaining high data transfer speeds through consistent, optimized connection geometries that can be replicated across multiple chips.
4Speed
If the number of through-electrodes increases with the number of layered core chips, then each chip can be connected independently, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the data transfer pathways into independent channels, each with its own latch circuit and through-electrode connection. This segmentation allows parallel operation of multiple core chips without requiring a proportional increase in total through-electrode count, as each segment operates independently with optimized resource utilization.
Solution Approach 2:
The latch circuit units act as intermediaries that manage and coordinate data flow from multiple core chips to the interface chip. This mediation allows multiple core chips to share the interface resources efficiently, reducing the total number of through-electrodes needed compared to a direct one-to-one connection scheme, while maintaining high-speed independent operation.
Data Source
AI summary
Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.