Semiconductor Storage Device Lever Shift Unit Bit Line Potential
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The Vcc/2 precharge system in DRAMs faces challenges with reduced power supply voltage, leading to delayed sense operations, increased power consumption, and area overhead in the ground precharge system, while the ground precharge system struggles with extra charge requirements and area increase.
Innovation Solution
A semiconductor storage device with a bit line precharge circuit that precharges bit lines to half the power supply potential, using level shifting capacitors to adjust the bit line potential and enhance the gate bias of the sense amplifier, thereby reducing power consumption and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply voltage is lowered in the Vcc/2 precharge system, then power consumption is reduced, but the sense operation is greatly delayed or may not be performed
Solution Approach 1:
The patent changes the precharge voltage parameter from Vcc/2 to ground (0V), which fundamentally alters the voltage relationship in the sense amplifier. This parameter change allows the sense amplifier to operate with full Vcc gate-source voltage while maintaining low power consumption, resolving the contradiction between reduced power supply voltage and sense operation speed
Solution Approach 2:
Instead of precharging the bit lines to Vcc/2 and relying on differential sensing, the patent inverts the approach by precharging to ground and using a level shift unit to create the necessary voltage differential. This inversion allows the sense amplifier to receive full Vcc bias voltage, ensuring fast sense operation even at lower power supply voltages
2Speed
If the ground precharge system is used to double the gate-source voltage, then high-speed operation is maintained, but power consumption and area are increased
Solution Approach 1:
The patent introduces a level shift unit as an intermediary component that translates the ground precharge system into a configuration that achieves both high speed and low power consumption. The level shift unit creates the necessary voltage differential without requiring the bit lines to be continuously held at high voltage, thereby reducing dynamic power consumption while maintaining fast sense operation
Solution Approach 2:
The level shift unit performs preliminary voltage adjustment on the bit lines before they enter the sense amplifier. By pre-establishing the appropriate voltage differential through the level shift unit, the sense amplifier can operate efficiently with full Vcc bias without requiring excessive power consumption, thus achieving both high speed and low power
3Speed
If the ground precharge system is used, then high-speed operation is maintained, but area overhead increases due to extra charge requirements
Solution Approach 1:
The level shift unit is designed to serve multiple functions: it creates the voltage differential for sensing, provides bias voltage to the sense amplifier, and enables operation with ground precharge. This multi-functionality eliminates the need for separate reference cells and additional charge storage structures, thereby achieving high-speed operation without the area overhead associated with traditional ground precharge systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed and stable sense operations without the need for a reference cell, minimizing power consumption and area overhead, while maintaining high-speed detection capabilities.
Implementation Method 1
the level shift unit includes level shifting capacitors, each of which having one electrode connected to each bit line, and forming one pair by two level shifting capacitors for each bit line pair
Data Source
AI summary
A semiconductor storage device includes a level shift unit that shifts level of potential of bit line pair BL, BLB when a sense amplifier starts to read potential of the bit lines. The level shift unit includes level shifting capacitors and a timing generator. Each of level shifting capacitors have one electrode connected to each bit line and form one pair by two level shifting capacitors for each bit line pair. The timing generator is connected to each of the other electrodes of the level shifting capacitors in common, and supplies a shift capacitor drive signal to a common node of the other electrodes, so as to change stored electricity amount of the level shifting capacitors at a predetermined timing.